Kabushiki Kaisha Toshiba

Kioxia Corporation

Renesas Technology Corp.

Renesas Electronics Corporation

Toshiba Memory Corporation

Hitachi Ulsi Systems Co., Ltd.

Mitsuhiro Noguchi

Akira Goda

Kenji Gomikawa

Minori Kajimoto

Hiraku Chakihara

Hiroyuki Kutsukake

Yoshiko Kato

Akio Nishida

Yuji Takeuchi

Takashi Aoi

Koji Hosono

Masaru Koyanagi

Yukihito Oowaki

Kousuke Okuyama

Masahiro Moniwa

Masato Endo

Dai Nakamura

Makoto Mizuno

Keiji Okamoto

Takeshi Shimane

Tadanori Yoshida

Yasuhiko Takahshi

Akira Nishiyama

Hiroaki Hazama

Masahiro Tadokoro

Hiroyuki Nitta

Haruhiko Koyama

Naonori Wada

Hiroshi Maejima

Masayuki Tanaka

Seiichi Mori

Takahiko Hara

Kenji Sawamura

Masayuki Akou

Shigeru Ishibashi

Daisaburo Takashima

Yasuhiko Matsunaga

Mizuki Ono

Shigehiko Saida

Mitsuhiko Noda

Tomoaki Shino

Daisuke Tsurumi

Hiroyasu Tanaka

Yoshio Ozawa

Toshitake Yaegashi

Kikuko Sugimae

Yoshitaka Tsunashima

Shinichi Watanabe

Yuichiro Mitani

Michiharu Matsui

Shoichi Watanabe

Takuro Homma

Aya Minemura

Masahiro Shimura

Yukio Nishida

Hiroshi Nishikizawa

Tetsuya Furukawa

Koji Sakui

Takuya Futatsuyama

Yasuhiro Shimura

Koji Kato

Takeshi Kamigaichi

Katsuaki Isobe

Tadashi Iguchi

Wataru Sakamoto

Koichi Fukuda

Junya Matsunami

Masami Aoki

Yoshitaka Kubota

Toshiki Hisada

Yasuyuki Baba

Toshinori Numata

Eiji Ito

Yasushi Nakajima

Hiroomi Nakajima

Hanae Ishihara

Susumu Yoshikawa

Shingo Nakajima

Tohru Maruyama

Kanae Uchida

Yuuichi Tatsumi

Hirokazu Tomino

Hideyuki Tabata

Hiromasa Yoshimori

Hideki Itai

Nobuaki Okada

Akimichi Goyo

Yu Suzuki

Ryuta Tezuka

A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

Non-volatile semiconductor storage device

A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.

Semiconductor memory device

A semiconductor device according to embodiments includes: a first conductivity-type first semiconductor layer set to a first potential; a second conductivity-type second semiconductor layer stacked on the first semiconductor layer and set to a second potential; an interlayer insulating film disposed on a main surface of the second semiconductor layer; a resistor disposed above the first semiconductor layer while interposing the second semiconductor layer and the interlayer insulating film therebetween; and a terminal electrically connected to the second semiconductor layer.

Semiconductor device

A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.

A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as Rand the radius of the second imaginary circle is denoted as R, R/Ris smaller than 1/cos(&#x3c0;/4).

Semiconductor device having a bonding pad area of a first wiring layer overlaps a bonding pad electrode of a second wiring layer

According to a certain embodiment, the nonvolatile semiconductor memory device includes: a first conductivity-type semiconductor substrate including a crushed layer on a back side surface thereof; a memory cell array disposed on a front side surface of the semiconductor substrate opposite to the crushed layer; and a first conductivity-type high voltage transistor HVP disposed on the semiconductor substrate and including a first conductivity-type channel, configured to supply a high voltage to the memory cell array. The first conductivity-type high voltage transistor includes: a well region NW disposed on the surface of the semiconductor substrate and having a second conductivity type; a source region and a drain region disposed in the well region; and a first conductivity-type first high concentration layer WTdisposed between the crushed layer of the semiconductor substrate and the well region and having a higher concentration than an impurity concentration of the semiconductor substrate.

Semiconductor memory device capable of suppressing leakage current

According to one embodiment, a semiconductor device includes a first semiconductor layer on a semiconductor substrate and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer is between the second semiconductor layer and the semiconductor substrate in a first direction. A first conductive layer is on the second semiconductor layer and contacting the second semiconductor layer. A third semiconductor layer is spaced from the second semiconductor layer in a second direction and connected to the first semiconductor layer. A second conductive layer is spaced from the first conductive layer in the second direction and connected to the third semiconductor layer. Each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer extends lengthwise in a third direction intersecting the first direction and the second direction.

A non-volatile semiconductor memory device includes a memory cell transistor having a memory cell capable of writing and erasing data, and a peripheral circuit that drives the memory cell which includes a first p-channel MOS transistor including a gate electrode that is formed on a semiconductor layer with a first gate insulation film therebetween, a channel region that is formed on a surface of the semiconductor layer and has a first peak dopant concentration, a source region and a drain region that have a second peak dopant concentration higher than the first peak dopant concentration, and overlap regions that extend between the channel region and the source region and the drain region, and also below a portion of the gate electrode, that have a third peak dopant concentration higher than the first peak dopant concentration and lower than the second peak dopant concentration by one order of magnitude or more.

Non-volatile semiconductor memory device and manufacturing method of p-channel MOS transistor

A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a first insulation material. A memory pillar extends through the first conductive layers. A hookup region is adjacent to the memory block and includes conductive layers stacked on the substrate at levels from the substrate that corresponds to the conductive layers in the memory block. An isolation region is between the memory block and the hookup region and includes first insulating layers of a second insulating material different than the first insulating material. Each first insulating layer is at a level from the substrate that corresponds to one of the first conductive layers and each first insulating layer is between one of the conductive layers in the memory block and one of the conductive layers in hookup region.

After forming a first film over the main surface of a semiconductor substrate, the first film is patterned, thereby forming a control gate electrode for a non-volatile memory, a dummy gate electrode, and a first film pattern. Subsequently, a memory gate electrode for the non-volatile memory adjacent to the control gate electrode is formed. Then, the first film pattern is patterned thereby forming a gate electrode and a dummy gate electrode.

Method of manufacturing a semiconductor device

Growing community of inventors

Yokohama, Japan

Mitsuhiro Noguchi