Spansion Llc.

Fujitsu Corporation

Fujitsu Vlsi Limited

Mitsuhiro Nagao

Kenji Shibata

Takaaki Furuyama

Kenta Kato

Masahiro Niimi

Masahiko Okura

Yoshihiro Takemae

Yasuharu Satoh

Yukihiro Nomura

Satoru Kawmoto

Stewart Wang

Yoshiyuki Ishida

Kenji Nagai

Shozo Kawabata

Kohji Shimbayashi

Satoru Sugimoto

Katherine Butler

Cheung Nga Tik

Operational information read out by a read-out sense amplifier () is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section () having a SRAM configuration and the second volatile memory section () configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section () in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (). Thus, the operational information is available in response to attributes of the operational information.

Non-volatile memory device

Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands.

Command control for synchronous memory device

The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions; program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in the memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state with respect to a memory region based on first prohibition information; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region based on second prohibition information with respect to the corresponding memory region.

Semiconductor device with double program prohibition control

Systems and methods for controlling memory devices are disclosed. In one embodiment, a memory system comprises a memory controller for forwarding a command signal and an address signal and for receiving and forwarding a data signal, and a first memory device for receiving the command signal and the address signal from the memory controller, where the first memory device comprises a first command judging circuit for receiving and forwarding the data signal and for decoding the command signal. The memory system further comprises a second memory device for receiving the command signal and the address signal from the memory controller, where the second memory device comprises a second command judging circuit for receiving and generating the data signal and for decoding the command signal. The command signal, the address signal and the data signal are commonly connected to the first memory device and the second memory device.

Shadow write and transfer schemes for memory devices

The present invention provides a semiconductor device and a method for controlling the semiconductor device, the semiconductor device including memory regions that include nonvolatile memory cells; program prohibition information units, the program prohibition information units storing program prohibition information to be used for determining whether to prohibit or allow programming in a plurality of memory regions corresponding to the program prohibition information units; a first prohibition information control circuit that prohibits a change of the program prohibition information from a program prohibiting state to a program allowing state with respect a memory region, the memory region is one of the plurality of corresponding memory regions, based on first prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program prohibiting state to a program allowing state with respect to the corresponding memory region; and a second prohibition information control circuit that prohibits a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region, based on second prohibition information to be used for determining whether to prohibit a change of the program prohibition information from a program allowing state to a program prohibiting state with respect to the corresponding memory region.

Program and erase disabling control of WPCAM by double controls

To provide a memory device and a password storing method thereof, according to which an improved security function is realized by resourcefully designing the storage position and/or storing order of password data stored in the memory device to prevent unauthorized password acquisition. The memory device makes a determination of whether or not rewriting and/or reading of data is permitted by verification of a password, the memory device comprising a plurality of partial memory areas which store a plurality of partial bit strings that comprise a bit string of the password, and wherein the plurality of partial memory areas are located apart from each other in a memory cell array.

Memory device and password storing method thereof

A semiconductor device includes: a memory cell array that includes non-volatile memory cells; a first memory region and a second memory region that are located in the memory cell array, the first memory region being protected during a protecting period, the second memory region being not protected; an address change circuit that changes an address in an address space of the first memory region and the second memory region in the memory cell array, to an address in an address space of the second memory region, during the protecting period; and a control circuit that prohibits access to the first memory region, and allows access to the second region, during the protecting period.

Semiconductor device and method of controlling the same

A nonvolatile storage including a plurality of blocks each serving as one unit in erasing operation and performs a plurality of erasing operations successively, the nonvolatile storage comprising: a volatile memory cell array for storing erase setting information on each block, the information indicating whether or not its associated block is a target to be erased; a write amplifier for writing the erase setting information in the volatile memory cell array; a first readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of the erasing operation; and a second readout amplifier for reading out the erase setting information on a target block from the volatile memory cell array upon start of readout operation.

Nonvolatile storage and erase control

A semiconductor device includes: memory regions that include non-volatile memory cells; disabling information memory units that correspond to the memory regions, each of the disabling information memory units storing first program disabling information indicating whether programming is to be disabled or enabled in each corresponding memory region; a program disabling information selection circuit that outputs second program disabling information for disabling programming in a corresponding memory region, regardless of the first program disabling information, when programming is disabled collectively in the memory regions in accordance with collective program disabling information indicating whether programming is to be disabled collectively in the memory regions, the program disabling information selection circuit outputting the first program disabling information as the second program disabling information when programming is not collectively disabled; and a program control circuit that disables or enables programming in the corresponding memory region in accordance with the second program disabling information.

In a memory cell array, aside from a normal-data storing region, a control-information storing region is also allocated, and the control-information storing region is composed of a predetermined number of control-information storing memory cells in each bit of control information, and same bit data is stored in the predetermined number of control-information storing memory cells, and the data is read out simultaneously at the time of reading out. When being read-out the control information, since data is read out simultaneously from the predetermined number of memory cells, the driving capacity of reading route when reading out is reinforced. Reading time of control information being read out at the time of turning on the power or initializing after resetting can be shortened, and the operation can be quickly transferred to normal access action.

Non-volatile memory device, and control method of non-volatile memory device

A redundancy judge circuit () includes a redundancy judge circuit address+1 controller (), an even-numbered redundant address judge section (), an odd-numbered redundancy judge section (), a redundant address ROM (), a redundant IOROM (), and a select section (). The redundancy judge circuit () may also include a memory cell circuit (), a read circuit (), and an address generator circuit (). With this structure, redundancy remedy can be conducted even during the burst operation due to the 2-bit prefetch, and slowing of the read operation speed can be prevented. Because it is possible to reduce the signal bus length of a decode signal bus in a column direction to substantially half and to reduce a decode signal bus region to substantially half, it is possible to prevent the wiring density in the wiring region of the decode signal bus from becoming high thereby preventing an increase in the read speed.

Semiconductor memory storage device and its control method

A verify sense amplifier () reads data from a non-volatile memory cell to be rewritten. The readout data is compared to expected data in a comparator circuit (). Upon completion of rewriting, the comparator circuit () outputs a match signal MCH. A selector () outputs a decode signal STR(i) or SWP(i) indicative of a volatile data retaining unit (), in correspondence with the non-volatile memory cell MC to be rewritten. According to a verify instruction signal PGV/ERV, the readout data read by the verify sense amplifier () is stored in the volatile data retaining unit (). Control is performed with a match signal MCH instead of the verify instruction signal PGV/ERV, thereby storing the data in the volatile data retaining unit () upon completion of rewriting. Therefore, there is no need to re-read operational information from the non-volatile storage.

Method and apparatus for setting operational information of a non-volatile memory

An address identifying memory block is match-compared with address information stored in a to-be-remedied block memory section in a block redundancy judge section. A redundant block select signal is outputted from the block redundancy judge section by judgment of address match. A memory block column select section selects a memory block column having a redundant memory block irrespective of an address signal as the redundant block select signal is activated if block redundancy is activated to output a memory block column select signal. A column redundancy memory section selects address information of column redundancy relating a redundant memory block arranged in a memory block column in accordance with the memory block column select signal.

Semiconductor memory storage device and a redundancy control method therefor

According to one aspect of the present invention, the flash memory comprises a memory region divided into a plurality of real banks, wherein from among the plurality of products which consists of a plurality of combinations of virtual banks having at least one real bank; and a combination of the top boot in which the most significant address is allocated to the boot bank having the boot sector and the bottom boot in which the least significant address is allocated to the boot bank, product information data are set in a product information record section, whereby any product can be configured.

Flash memory capable of changing bank configuration

A DRAM (Dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

Growing community of inventors

Kasugai, Japan

Mitsuhiro Nagao