Kabushiki Kaisha Toshiba

Mitsuhiro Koga

Hiroshi Shinya

Munehiro Yoshida

A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O buffer outputs N-bit data. The I/O buffer inputs N-bit data to the read/write buffer, and the read/write buffer outputs N-bit data to the I/O buffer. The memory cell array inputs up to M&#xd7;N-bit data to the read/write buffer, and the read/write buffer outputs up to M&#xd7;N-bit data to the memory cell array. The read/write buffer writes a variable number of bits to the memory cell array (N is a natural number equal to or larger than 1, and M is a natural number equal to or larger than 2).

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a memory cell array, an error checking and correcting (ECC) circuit which performs an error checking and correcting operation for readout data read out from the normal data storing portion at data readout time during read latency and an I/O buffer. The memory cell array includes a normal data storing portion and a parity data storing portion. The normal data storing portion stores data for use in a normal data write and a normal data read. The parity data storing portion stores parity data for use in error checking and correcting. The EEC circuit carries out error checking and correcting read data read out from the normal data storing portion, during read latency cycle at a data read operation. The I/O buffer outputs the read data error checked and corrected by the ECC circuit, after the read latency cycle has lapsed.

Semiconductor integrated circuit device and error checking and correcting method thereof

A semiconductor memory device is disclosed which comprises a cell array including a normal data section used for normal data write and read and a parity data section used for check data write and read, the check data being for execution of error check of data as read out of the normal data section, a data buffer for temporal stage of read data from the cell array and write data into the cell array, and an ECC circuit for generating the check data to be stored in the parity data section from write data as input during data writing, and for performing error check and correction of data read out of the normal section based on the data read out of the normal data section and the check data read out of said parity data section during data reading. N-bit parallel data transfer is performed between the data buffer and normal data section whereas m-bit parallel data transfer is done between the data buffer and external input/output terminals (where m and n are integers satisfying m&#x3c;n).

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Yokohama, Japan

Mitsuhiro Koga