Sharp Kabushiki Kaisha Corporation

Yazaki Corporation

Tohoku University

Mitsuhiro Kikuta

Alberto Oscar Adan

Tadahiro Ohmi

Akinobu Teramoto

Takanori Watanabe

Hiroo Yabe

In a power IC device, a surface layer channel CMOS transistor and a trench power MOS transistor are formed on the same chip. In one embodiment, a source region of the trench power MOS transistor is arranged at the same level as a gate electrode of the surface layer channel CMOS transistor. Thus, the power IC device and a method for manufacturing the power IC device are provided for reducing manufacturing cost in the case of forming the trench power MOS transistor and the surface layer channel CMOS transistor on the same chip.

Power IC device and method for manufacturing same

In one embodiment of the present invention, a power IC device is disclosed containing a power MOS transistor with a low ON resistance and a surface channel MOS transistor with a high operation speed. There is also provided a method of manufacturing such a device. A chip has a surface of which the planar direction is not less than &#x2212;8&#xb0; and not more than +8&#xb0; off a silicon crystal face. The p-channel trench power MOS transistor includes a trench formed vertically from the surface of the chip, a gate region in the trench, an inversion channel region on a side wall of the trench, a source region in a surface layer of the chip, and a drain region in a back surface layer of the chip. The surface channel MOS transistor has an inversion channel region fabricated so that an inversion channel current flows in a direction not less than &#x2212;8&#xb0; and not more than +8&#xb0; off the silicon crystal direction.

Power IC device and method of manufacturing same

Growing community of inventors

Kyotanabe, Japan

Mitsuhiro Kikuta