Denso Corporation

Nippondenso Co., Ltd.

National Institute of Advanced Industrial Science and Technology

Mitsuhiro Kataoka

Tsuyoshi Yamamoto

Rajesh Kumar

Shigeki Takahashi

Yuji Kimura

Susumu Sobue

Norihito Tokura

Yutaka Tomatsu

Yuichi Takeuchi

Yoshifumi Okabe

Yuuichi Takeuchi

Florin Udrea

Eiichi Okuno

Kunihiko Hara

Tsunenobu Kimoto

Masami Naito

Naoto Okabe

Hiroyuki Matsunami

Andrei Mihaila

Suhail Rashid Jeremy

Kazukuni Hara

Satoshi Yamasaki

Shoichi Onda

Hiromitsu Kato

Daisuke Takeuchi

Yasuo Kitou

Jun Kojima

Takamasa Suzuki

Shoichi Kawai

Eiji Kitaoka

Yuuchi Takeuchi

A heat transfer device that includes a thermionic power generator, a wiring, a load circuit, and a switch circuit. The thermionic power generator includes an emitter electrode and a collector electrode facing each other with an inter-electrode gap distance, and converts heat energy into electric energy by capturing, with the collector electrode, a thermoelectron that is emitted from the emitter electrode. The wiring electrically connects the emitter electrode and the collector electrode. The load circuit is connected to an electric current path of by wiring between the emitter electrode and the collector electrode. The switch circuit switches between an ON state and an OFF state.

Heat transfer device, temperature controller, internal combustion engine, exhaust system thereof, and melting furnace

A thermionic power generator includes an emitter generating thermions and a collector collecting the thermions. The emitter includes an emitter substrate having an electric conductivity, a low resistance layer stacked to the emitter substrate and made of an n-type diamond semiconductor that includes phosphorus as a donor, and an electron emission layer stacked to the low resistance layer and made of an n-type diamond semiconductor that includes nitrogen as a donor. The collector includes a collector substrate having an electric conductivity and is disposed opposite to the emitter via a clearance. The electron emission layer has a thickness equal to or less than 40 nm.

Thermionic power generator

In a method of manufacturing an electrode of a thermionic converter, a carbide layer is formed on a base material by a vapor synthesis, an N-type diamond layer doped with a donor impurity is formed on the carbide layer by a vapor synthesis, and a surface of the N-type diamond layer is terminated with hydrogen. The base material is made of a metal, and the carbide layer is made of a metal carbide.

Thermionic converter and manufacturing method of electrode of thermionic converter

A thermionic generator for converting thermal energy to electric energy includes: an emitter electrode for emitting thermal electrons from a thermal electron emitting surface when heat is applied to the emitter electrode; a collector electrode facing the emitter electrode spaced apart from the emitter electrode by a predetermined distance, and receiving the thermal electrons from the emitter electrode via a facing surface of the collector electrode; and a substrate having one surface. The emitter electrode and the collector electrode are disposed on the one surface of the substrate, and are electrically insulated from each other. The thermal electron emitting surface and the facing surface are perpendicular to the one surface.

Thermionic generator

A thermionic converter for converting thermal energy to electrical energy includes an emitter and a collector. The emitter emits thermionic electrons upon receipt of heat from a heat source. The emitter is made of a first semiconductor material to which a first semiconductor impurity is doped with a first concentration. The collector is spaced and opposite to the emitter to receive the thermionic electrons emitted from the emitter so that the thermal energy is converted to electrical energy. The collector is made of a second semiconductor material to which a second semiconductor impurity is doped with a second concentration less than the first concentration.

Thermionic converter

A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is &#x3c;11-20&#x3e;. A trench is formed on the SiC to have a stripe structure extending toward a &#x3c;11-20&#x3e; direction. An SiC epitaxial layer is formed on an inside surface of the trench.

Silicon carbide semiconductor device

A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

Gate wiring layout for silicon-carbide-based junction field effect transistor

A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.

In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped-source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.

P-channel MOSFET semiconductor device having a low on resistance

In a semiconductor device having a substrate, a p-type semiconductor layer, an n-type channel well region, a p-type lightly doped source region, and a source electrode formed on the substrate in this order, a p-type heavily-doped source region, an impurity concentration of which is higher than that of the lightly-doped source region, is formed in a surface region of the lightly-doped source region. The source electrode is formed to contact the heavily-doped source region. As a result, a punch through phenomenon between the p-type source region and the p-type semiconductor layer through the n-type channel well region can be prevented without increasing in the On resistance of the semiconductor device.

Method of producing a semiconductor device

A manufacturing method of a vertical type MOSFET, which can suppress vaporization of impurity from a semiconductor substrate and prevent variation in carrier density of the channel, is disclosed. The vertical type MOSFET is formed by forming a local oxide film to form a concavity on the element surface, removing the local oxide film by wet-etching technique, forming the gate oxide film at the sidewall of the concavity by thermal oxidation, and forming a gate electrode. Further, a polycrystalline silicon is formed on a back surface of the semiconductor substrate before removing the local oxide film. Accordingly, since the polycrystalline silicon is not removed when removing the local oxide film, vaporization of impurity from the semiconductor substrate is suppressed during the thermal oxidation for forming the gate oxide film, thereby preventing change in the carrier density of the channel.

Manufacturing method of semiconductor device

A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

Semiconductor device

A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

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Kariya, Japan

Mitsuhiro Kataoka