Fujitsu Corporation

Mitsuhiro Higashiho

Satoshi Eto

Masato Matsumiya

Toshikazu Nakamura

Ayako Kitamoto

Kuninori Kawabata

Masato Takita

Toru Koga

Hideki Kano

Masao Taguchi

Yoshinori Okajima

Koichi Nishimura

Hajime Sato

Hideki Kanou

Shusaku Yamaguchi

Shigemasa Ito

Masami Nakashima

In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuitfor propagating either a refresh address ADD (Ref) from a refresh counterat a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuitfor discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuitfor outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuitis switched only at a time of a mode change.

Semiconductor memory device, control method thereof, and control method of semiconductor device

Semiconductor memory device control method thereof, and control method of semiconductor device

There are provided a semiconductor memory device and a refresh control method thereof to realize a refresh operation without any problem for external accesses while realizing low current dissipation operations for executing the refresh operation in separation from external access operation, in which the refresh operation is inhibited during execution of the external accesses. During this period, the internal operation in the refresh operation is controlled for the first refresh-operation-start request, but the internal operation for the second and subsequent refresh operation start requests is inhibited. Even when a plurality of refresh-operation-start requests are outputted previously while the refresh operation is inhibited during the external access operation, only the internal operation is not executed previously and the refresh operations after completion of the external access operation can surely be executed.

Refresh control method of semiconductor memory device and semiconductor memory device comprising the same control method

In a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of an internal signal for every operation mode by required minimum control, a control method thereof, and a control method of a semiconductor device, there are provided an address switching circuit for propagating either a refresh address ADD (Ref) from a refresh counter at a time of a refresh mode or an external address ADD (R/W) at a time of data-input/output mode as internal address ADD (INT), a mode discriminating circuit for discriminating between a refresh operation requesting signal REQ (Ref) and a data input/output requesting signal REQ (R/W) and for outputting a mode discriminating signal M, and a switch holding circuit for outputting a switch change-over signal SW in accordance with the mode discriminating signal M, and the connection of the address switching circuit is switched only at a time of a mode change.

In a synchronous semiconductor memory device which provides the refresh cycle optimum for charge retention characteristics without being influenced by production variations, and without requiring much test time to measure characteristics before adjustment of the refresh time, and enables reduction of current consumption in a refresh operation, an output signal from an active pointer circuit which is a phase comparison signal from a DLL circuit is output as a digital signal, and the digital signal is converted by a D/A converter circuit to an analog signal for determining the current value of a constant current circuit, and then, in a measured cycle modification circuit constituting the constant current circuit, the current value responsive to the voltage value of this analog signal is set as the driving current of an oscillation circuit which is a refresh cycle measurement circuit so as to control a driving capability, thereby an oscillation signal for self-refreshing is output.

Synchronous semiconductor memory device and refresh method thereof

A semiconductor memory operates in a write mode and a read mode. The memory includes memory cells, pairs of bit lines connected to the memory cells, sense amplifiers having first and second I/O terminals connected to the bit lines, column selection gates connected to the associated sense amplifiers, and a control circuit. The control circuit controls the sense amplifiers and the column selection gate, so that selected column selection gate turns on before the sense amplifiers are activated during the write mode. The write data is applied to the first I/O terminals of the sense amplifiers. The semiconductor memory thus produced according to the present invention has a reduced circuit size.

Semiconductor memory and method for controlling the same

A semiconductor memory device includes a core area formed of memory blocks each having a relaxed sense amplifier arrangement, a data bus including data bus lines corresponding to the memory blocks, a plurality of input/output terminals provided in number corresponding to the data bus lines forming the data bus, and a data path switch circuit provided between the data bus the input/output terminals for providing interconnection paths between the input/output terminals and the data bus lines, wherein the data path switch circuit switches a part of the interconnection paths in response to a switch control signal such that the input/output terminals are connected respectively to predetermined memory cells located at respective, predetermined physical locations in any of the memory blocks.

Semiconductor memory device having a relaxed pitch for sense amplifiers

A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.

Variable delay circuit and semiconductor integrated circuit device

A synchronous semiconductor memory apparatus is capable of activating an input buffer circuit only in a required operating cycle and achieving low current consumption without degrading high speed response properties of an input buffer. When combination of control signals (Control) such as /CS, /RAS, /CAS, /WE and the like is directed to active command (ACTV), read command (READ, READA), write command (WRITE, WRITEA), mode register command (MRS), pre-charge command (PRE) and the like, a latch operation is dynamically performed for input from address pins. In this way, in the case where a signal iRAS is set at a low level, a latch signal aCLK is output to the rising edge of a signal iCLK, thereby latching addresses Add or the like. Alternatively, in the case where a signal iRAS or iCAS is set at a low level, the latch signal aCLK is output to the rising edge of the signal iCLK, thereby latching addresses Add or the like.

Synchronous semiconductor memory apparatus and input information latch control method thereof

A semiconductor memory device includes a memory cell connected to a bit line and a word line, a bit line precharge circuit which precharges the bit line to a ground voltage, and a word decoder which sets the word line to a negative voltage when the word line is not selected.

Semiconductor memory device

A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.

Semiconductor memory device with efficient layout

An electronic device includes a first circuit which refers to an external clock and thus produces a first internal clock, and a second circuit which refers to the first internal clock and thus produces a second internal clock. The first circuit has a first phase error between the external clock and the first internal clock, and the second circuit has a second phase error between the first internal clock and the second internal clock. The first phase error has a sign reverse to that of the second phase error.

Electronic device and semiconductor memory device using the same

A charge-pump type booster circuit has a first capacitor, a power source applying unit, a transfer gate, a second capacitor, a switching unit, and a precharge circuit. The first capacitor is used to boost an output voltage, the power source applying unit is used to apply a first power supply voltage to an output terminal of the first capacitor. The transfer gate is used to transfer the boosted output voltage, and the second capacitor is used to boost a gate voltage of the transfer gate. The switching unit is used to control an input voltage of the second capacitor, and the precharge circuit is used to apply a specific high voltage to a control terminal of the transfer gate. Therefore, a sufficient high-voltage output (super-high power supply voltage) can be surely generated by using a low voltage (general high power supply voltage).

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Kasugai, Japan

Mitsuhiro Higashiho