Mitsubishi Denki Kabushiki Kaisha

Panasonic Corporation

Renesas Technology Corp.

Mitsuhiro Hamada

Jun Ohtani

Kenichi Yasuda

Osamu Hashimoto

Shuji Mizokuchi

Masaaki Tanimura

Katsuyoshi Jokyu

Tatsumi Kumekawa

Kouichi Tomita

A body contact layeris formed on the side of a recessed structureas well as in the bottom of the recessed structure, so that a contact area between the body contact layerand a well layeris increased and the amount of dopant implanted to the body contact layeris suppressed.

Semiconductor device and method of manufacturing the same

The present invention provides a semiconductor apparatus having high reliability with respect to a withstand voltage, leakage characteristics, etc. by disposing a structure of preventing stress occurring by metal wiring from directly acting on a trench relating to the semiconductor apparatus having a trench gate. The semiconductor apparatus of the invention includes a semiconductor substrate including a semiconductor layer having a predetermined impurity concentration, a trench gate formed in the semiconductor layer by filling a stripe-shaped trench by a conductor layer on which surface and interface a gate oxide film is formed, an insulating film covering a surface of the semiconductor layer and having a source contact opening, a source region formed in the semiconductor layer, a source electrode formed on the surface of the semiconductor layer so as to electrically connect to the source region through the source contact opening, a gate peripheral wiring connected to the trench gate at a peripheral edge part of the trench gate, a gate electrode separately formed from the source electrode, formed above the surface of the semiconductor layer and connected to the gate peripheral wiring and a drain electrode formed on an surface of the semiconductor substrate opposite to the surface of the semiconductor layer, wherein the trench gate is formed so as to avoid a corner portion of the source contact opening of the source electrode.

Semiconductor apparatus

While a semiconductor device is provided with a plurality of element electrodesformed on a semiconductor elementand a plurality of lead terminal electrodesformed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodesto at least one electrode among the above-described lead terminal electrodes; the above-described coupling conductor is manufactured by a first conductorand a second conductor, the major components of which are metals; the first conductorhas been electrically connected to the second conductor; and the element electrodesand the lead terminal electrodeshave been electrically connected to the second conductorrespectively.

Semiconductor device including a coupling conductor having a concave and convex

An apparatus to be inspected is mounted on one surface of a socket board. An auxiliary inspecting apparatus for adjusting timing of write signals transmitted from a semiconductor inspecting apparatus is mounted on the other surface of the socket board. Input/output (I/O) pins of the auxiliary inspecting apparatus are connected to corresponding I/O pins of the inspected device via through holes in the socket board on a one-to-one basis. This semiconductor inspecting method is thus capable of easily suppressing the delay difference between a plurality of signals output from the semiconductor inspecting apparatus.

Semiconductor inspecting system for inspecting a semiconductor integrated circuit device, and semiconductor inspecting method using the same

Row faulty bit storage memory corresponding to a spare row circuit and a column faulty bit storage memory corresponding to a spare column circuit are provided independently of each other, and faulty bits of these faulty bit storage memories are counted by a row faulty bit counter and a column faulty bit counter, respectively. Repairability of the faulty row and repairability of the faulty column are determined using the row faulty bit storage memory and the column faulty bit storage memory. A time required for determining repairability of the faulty bit of a semiconductor memory is reduced, and a storage capacity of the faulty bit storage memory is reduced.

Testing apparatus for semiconductor memory device

A first delay circuit for delaying a data signal IND output from a memory circuit and a second delay circuit for delaying a strobe signal INS, and a latch circuit for latching data according to the outputs of the first and the second delay circuits are provided as a test circuit inside a DDR SDRAM. A tester can observe results of latching by the latch circuit to facilitate determination whether the data signal and the strobe signal have a correlation adapted to a standard. Accordingly, such a DDR SDRAM can be provided that is capable of conducting an examination whether the device meets a tDQSQ standard defining a correlation between the strobe signal DQS and the data signal DQ with ease.

Semiconductor memory device enabling test of timing standard for strobe signal and data signal with ease, and subsidiary device and testing device thereof

In a semiconductor device including banks A and B, testing and redundancy analysis of the bank B are first carried out by using a conventional tester, and redundancy replacement is carried out. Then, the bank A is tested by a BIST circuit and the test result of each bit is written to the bank B. By using the bank B as a memory for defect analysis, a tester connected to the semiconductor device while testing the bank A does not need a large capacity analysis memory. Thus, an inexpensive redundancy analysis system can be provided.

Growing community of inventors

Hyogo, Japan

Mitsuhiro Hamada