Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Denki Kaisha Kitaitami Seisakusho

Mitsuhiro Deguchi

Michio Komoda

Ichiro Tomioka

Nobuyuki Osawa

A memory cell for an associative storage memory device includes a transmission gate which is rendered conductive or non-conductive in response to a potential on a word line for transferring information between an information hold circuit and a bit line or between the information hold circuit and an inverted bit line. Match line are precharged to ground and supply potentials, respectively, and, thereafter, a retrieval circuit compares information on the bit line or inverted bit line with information held in the information hold circuit and produces a control signal to control the potentials on the match lines in accordance with the result of comparison. After the match lines are precharged, a gating circuit is rendered conductive in response to potentials on output control line and inverted output control line to thereby couple the control signal to the match lines.

Associative storage memory

A semiconductor logic circuit includes a number of gate circuits and a voltage supply. Each of the gate circuits includes a series circuit comprising the same number of transistors of one conductivity type connected in series, and a parallel circuit comprising the same number of transistors of a different conductivity type connected in parallel. The series and parallel circuits are connected in series between a voltage supply and ground. The semiconductor logic circuit includes the same number of input pins, and an output pin connected in common to all of the gate circuits. Each of the input pins is connected to a different one of the transistors in the series circuit and to a different one of the transistors in the parallel circuit of each of the gate circuits. The control electrode of the k-th transistor from the end of each series circuit closer to the voltage supply is connected to a different one of the input pins, and the control electrode of the m-th transistor from the end of each parallel circuit closer to the input pins is connected to a different one of the input pins.

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Itami, Japan

Mitsuhiro Deguchi