Shinko Electric Industries Co., Ltd.

Shinko Electric Electric Industries Co., Ltd.

Mitsuhiro Aizawa

Kei Murayama

Michio Horiuchi

Yasue Tokutake

Yuichi Matsuda

Ryo Fukasawa

Mitsutoshi Higashi

Akinori Shiraishi

Kazutaka Kobayashi

Kiyoshi Oi

Shota Miki

Koji Hara

Naoki Kobayashi

Yasuyoshi Horikawa

Naohiro Mashino

Yoshihiro Ihara

Hiroshi Shimizu

Kazuyuki Kubota

Katsunori Yamagishi

Mina Iwai

Koyuki Kawakami

Amane Kaneko

A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin formed from a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the encapsulation resin. The covering resin is disposed on the upper surface of the upper substrate and covers a side surface of the wiring layer.

Semiconductor device

A composite wiring substrate includes a first wiring substrate including a first connection terminal, a second wiring substrate including a second connection terminal facing the first connection terminal, and a joint material joining the first connection terminal and the second connection terminal. The first outline of the first connection terminal is inside the second outline of the second connection terminal in a plan view. The joint material includes a first portion formed of an intermetallic alloy of copper and tin, and contacting each of the first connection terminal and the second connection terminal, and a second portion formed of an alloy of tin and bismuth, and including a portion between the first outline and the second outline in the plan view. The second portion contains the bismuth at a higher concentration than in the eutectic composition of a tin-bismuth alloy, and is separated from the second connection terminal.

Composite wiring substrate and semiconductor device

A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.

Wiring substrate, stacked wiring substrate, and manufacturing method of wiring substrate

A battery includes a supporting substrate, resin layers, and a plurality of cells. Each resin layer includes a first resin and has 0.5 MPa to 10 MPa in tensile strength. The cells are stacked on the supporting substrate with the resin layers between the cells.

Battery and method for producing the same

A probe card includes a wiring substrate including an opening portion and a connection pad arranged on an upper face of the wiring substrate located on the periphery of the opening portion, a resin portion formed in the opening portion of the wiring substrate, and the resin portion formed of a material having elasticity, a contact terminal arranged to protrude from the lower face of the resin portion, and wire buried in the resin portion and connecting the contact terminal and the connection pad, wherein the contact terminal is formed of an end part of the wire, and is formed integrally with the wire.

Probe card having a wiring substrate

A probe card includes a wiring substrate including an opening portion, a first connection pad, and a second connection pad arranged in an opposite area to the first connection pad, a resin portion formed in the opening portion, a first wire buried in the resin portion, in which one end is connected to the first connection pad and other end constitutes a first contact terminal, and a second wire buried in the resin portion, in which one end is connected to the second connection pad and other end constitutes a second contact terminal, wherein the first and second wires extend on one line, and the first and second contact terminals are arranged on the one line, and the first and second contact terminals are gathered to be separated such that the first and second contact terminals touch one electrode pad of a text object with a pair.

Probe card

A probe card, includes, a wiring substrate having an opening portion and including a first connection pad and a second connection pad, the first connection pad being arranged at a periphery of the opening portion, the second connection pad being arranged to be adjacent to the first connection pad, a resin portion formed inside the opening portion of the wiring substrate, a first wire buried in the resin portion and having one end connected to the first connection pad and the other end constituting a first contact terminal protruding from a lower face of the resin portion, and a second wire buried in the resin portion and having one end connected to the second connection pad and the other end constituting a second contact terminal protruding from a lower face of the resin portion.

An interposer includes a wiring member including a first inorganic substrate, a reinforcement member including a second inorganic substrate, and an adhesive part interposed between the wiring member and the reinforcement member. Each of the first and second inorganic substrates includes first and second surfaces. Multiple inorganic insulating layers formed on the first surface of each of the first and second inorganic substrates have the same layer configuration and are arranged symmetrically in a vertical direction with the adhesive part centered therebetween. An inorganic insulating layer and an organic insulating layer formed on the second surface of each of the first and second inorganic substrates have the same layer configuration and are arranged symmetrically in the vertical direction with the adhesive part. An organic insulating layer formed on the second surface of each of the first and second inorganic substrates is an outermost insulating layer.

Interposer and electronic component package

There is provided a wiring board. The wiring board includes: a first insulating layer; a plurality of wiring patterns on the first insulating layer so as to be spaced apart from each other; a plating layer on at least one of the wiring patterns; a second insulating layer containing silicone therein and having an opening, wherein an outermost surface of the plating layer is exposed from the opening and serves as a connection pad; and a silica film on the outermost surface of the plating layer.

Wiring board and light emitting device

There is provided a wiring board for mounting a light emitting element thereon. The wiring board includes: an insulating layer; a wiring pattern on the insulating layer; a reflecting layer on the insulating layer to cover the wiring pattern, wherein the light emitting element is to be mounted on a surface of the reflecting layer; and a silica film on the surface of the reflecting layer.

A plurality of chip sealing bodies stacked on a wiring substrate with a connection terminal. The chip sealing body includes a semiconductor chip having a semiconductor integrated circuit, a pad and a conductive connecting material, and a resin sealing the semiconductor chip. The chip sealing body is shaped into a cubic form in which a portion of the conductive connecting material except an end portion located on an external device side and all surfaces of semiconductor chip is sealed by the resin and the end portion of the conductive connecting material located on the external device side is exposed from the cubic form. A conductive bonding wire connects the end portions of the conductive connecting materials and the connection terminal respectively. A resin sealing material seals the plurality of chip sealing bodies, the conductive bonding wire, and the wiring substrate.

Semiconductor chip stacked body and method of manufacturing the same

In a semiconductor inspecting device having a contact to be electrically connected to an electrode pad formed in a semiconductor device which is an object to be measured, and a substrate provided with the contact, the contact is provided obliquely to a main surface of the substrate.

Semiconductor inspecting device

A method for production of a semiconductor package which enables uniform conduction processing for all through holes covered by the conduction processing without being limited to any specific structure, is free from surface relief shapes and internal voids, and enables conduction processing simply, in a short time, at a low cost utilizing existing facilities, wherein the conduction processing of the through holes includes a step of press fitting a conductor into the through holes by a ball bonder and a step of flattening the exposed heads of the press-fit conductors by coining.

Method for production of semiconductor package

An assembly of semiconductor devices, wherein the device comprises a chip with electrodes on one side for electrical connection with an external circuit, and a flexible base comprising an insulation film having an inner opening and outer openings outside the inner opening, and the conductor pattern comprising a plurality of inner leads having an end extending to the inner opening of the film, and the outer leads being positioned to bridge the outer opening of the film; and the chip being mounted on the flexible base by bonding the lead-out electrodes thereof to the ends of inner leads, and wherein the devices are assembled to be connected with each other through the outer leads of semiconductor devices which are adjacent to each other, and the semiconductor chips, which face a substrate on which the assembly is to be mounted, have external connection electrodes, on which an external connection terminal for mounting is provided.

Growing community of inventors

Nagano, Japan

Mitsuhiro Aizawa