Hitachi Engineering Co., Ltd.

Renesas Technology Corp.

Hitachi, Ltd.

Other

Hitachi Engineering Ltd

Mitsuhiko Okutsu

Yasuyuki Saito

Naoki Yada

Tadaaki Kariya

Katsunori Koike

Yasushi Shibatsuka

Tatsuo Shimura

Shoji Sato

Mitsuru Hiraki

Kenichi Fukui

Kouji Kawamoto

Syuzoh Kaneko

Yasuhiro Mashiko

Kenji Abe

Kazuyoshi Masuda

A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.

Semiconductor integrated circuit

In view of controlling overshoot when the power supply is inputted without increase in the area occupied with a chip in a voltage generating circuit mounted over a semiconductor integrated circuit, an internal voltage generating circuit comprises a voltage generating circuit for generating a second voltage from a first voltage supplied from outside, and an output buffer for generating a third voltage corresponding to the second voltage. The third voltage is used as the operation power supply of the internal circuit. Moreover, a first switch for enabling an output node of the second voltage to become conductive to the predetermined potential and a control circuit for turning ON the first switch for the predetermined period in response to input of the first voltage are also provided. An output terminal of the output buffer is not clamped but an output of the voltage generating circuit in the preceding stage is clamped to the predetermined voltage. The transistor of the first switch for clamping the voltage may be remarkably reduced in size in comparison with an output transistor of the output buffer. Accordingly, the area occupied by the chip is not enlarged.

A voltage boost circuit operates by applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and, in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of said booster capacitance, a pulse width of the one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.

Voltage booster circuit apparatus

A voltage boost circuit operates by: applying a power supply voltage to both terminals of a booster capacitance in a discharge period; and in a charging period which follows the discharge period, by turning on a switching circuit in response to application of one shot pulse thereto, a power supply voltage is applied to one terminal of said booster capacitance, a ground potential is applied to the other one terminal thereof, wherein, during the charging of the booster capacitance, a pulse width of said one shot pulse is adjusted in accordance with a magnitude of the power supply voltage.

Voltage booster circuit control method

A driving circuit suitable for driving a capacitive load such as an EL display panel is disclosed, which comprises a first power source terminal; a second power source terminal; an output terminal, with which a capacitive load is connected; a source side thyristor connected between the first power source terminal and the output terminal, and supplying current to the load; a sink side thyristor connected between the second power source terminal and the output terminal and drawing-out current from the load; and a control section connected between the first power source terminal and the second power source terminal and ON-OFF controlling the source side thyristor and the sink side thyristor through a circuit arrangement coupled between the control circuit and the gates of the thyristors.

Circuit for driving a capacitive load utilizing thyristors

A capacitive load driving apparatus which has a plurality of first switching elements connected between a plurality of parallel loads and a first power source terminal for switching currents which charge the loads. There is furthermore provided a plurality of bipolar transistors connected between connecting points (of the first switching elements and the loads) and a second power source terminal for discharging charges stored in the loads and a plurality of second switching elements connected between a third power source terminal and bases of the bipolar transistor, respectively, for switching base currents supplied from the third power source terminal to the bipolar transistors. In addition, the capacitive load driving apparatus has a logic circuit connected to an input terminal for providing driving signals which turn off selectively one or all of the second switching elements in accordance with a signal from the input terminal, and it has a resistor connected between the third power source terminal and the second switching elements.

Capacitive load driving apparatus

A device for driving a capacitive load, comprising a first switching element responsive to an external control signal for selectively conducting a charge current therethrough to the load, a second switching element responsive to the external control signal for conducting a discharge current from the load and a generator for generating from the discharge current a cutoff signal to be applied to the first switching element to ensure turn-off of the latter.

Capacitive load driving device

A reference voltage circuit in which an output reference voltage is stabilized against variations in power source as well as in transistor current amplification factor h.sub.FE. In a reference voltage circuit comprising a DC power source connected to an output terminal, first and second resistors with their respective one ends commonly connected to the output terminal, a first NPN transistor with its collector shorted with its base and connected to the other end of the first resistor and its emitter grounded, a second NPN transistor with its collector connected to the other end of the second resistor and its base connected to the collector of the first NPN transistor, a third resistor connected between the emitter of the second NPN transistor and the ground, and a third NPN transistor with its collector connected to the output terminal, its base connected to the collector of the second NPN transistor and its emitter grounded, there are further provided a fourth resistor connected between the collector of the third NPN transistor and the output terminal and a PNP transistor with its base connected to the collector of the third NPN transistor, its emitter connected to the output terminal and its collector grounded.

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Mito, Japan

Mitsuhiko Okutsu