Kabushiki Kaisha Toshiba

Oki Electric Industry Co., Ltd.

Oki Data Corporation

Mitsuhiko Kitagawa

Ichiro Omura

Akio Nakagawa

Yoshiaki Aizawa

Masakazu Yamaguchi

Kazuya Nakayama

Yoshio Yokota

Takashi Shinohe

Norio Yasuhara

Tomoki Inoue

Minami Takeuchi

Kazuo Watanuki

Hiroshi Iwai

Takashi Nishimura

Tsuneo Ogura

Toshihiko Iinuma

Tetsujiro Tsunoda

Michiaki Hiyoshi

Hiroomi Nakajima

Akihiko Osawa

Kouhei Morizuka

Yasuhiro Katsumata

Shigeru Hasegawa

Yoshinari Uetake

Kazunobu Nishitani

Kazumi Inou

Hironobu Kon

Tomoko Matsudai

Kazuya Yamamoto

Syotaro Ono

Yusuke Kawaguchi

Akira Nakayama

Hiromichi Ohashi

Yoshiro Baba

Hideo Matsuda

Tomiya Sasaki

Takashi Fujiwara

Shuichi Fujikura

Takuma Hara

Masami Iwasaki

Masaru Ishizuka

Yoshio Kamei

Dai Karasawa

Asako Matsuura

Shigeki Monma

Yoshinoro Iwano

Yasuyuki Yokono

Ryujiro Saso

Kazuo Watanuki, Deceased

Yoshinori Iwano

A load controller includes a control device, a switching device, an arc suppression circuit, and a control section. The control device is provided on an electric power supply path between first and second terminals coupled to an alternating-current electric power source, and controls electric power supply to a load provided on the electric power supply path. The switching device is provided on the electric power supply path and is to be in an open state or a closed state. The arc suppression circuit is to suppress discharge at the switching device. The arc suppression circuit is to be set to an enabled state or a limited state. The control section controls operation of the control device, the switching device, and the arc suppression circuit. The control section varies the arc suppression circuit from the limited state to the enabled state after bringing the switching device into the closed state.

Load controller and image forming apparatus

A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to the fifth semiconductor region.

Semiconductor device

A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.

Semiconductor device and method for driving same

According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.

Semiconductor device having diode characteristic

A semiconductor device includes a first semiconductor region of a second conductivity type, and a second semiconductor region of a first conductivity type. A third semiconductor region of a first conductivity type is selectively provided on the second semiconductor region. A fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the second conductivity type are selectively provided on the third semiconductor region. A first electrode is provided on a second insulating film within the second semiconductor region. A second electrode is in contact with the fifth semiconductor region and the third semiconductor region. The sixth semiconductor region is provided on the second semiconductor region at least in a portion thereon other than the area where the third semiconductor region is provided. The sixth semiconductor region is not in contact with the second electrode.

A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a first control electrode, a first electrode, a second control electrode, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a first insulating film. The first control electrode is provided on or above the first semiconductor region. The first electrode is provided on the first control electrode. The second control electrode is provided on or above the first semiconductor region and includes a first portion which is beside the first control electrode and a second portion which is provided on the first portion and beside the first electrode. The second semiconductor region is provided on the first semiconductor region. A boundary between the first semiconductor region and the second semiconductor region is above the lower end of the first electrode.

In one embodiment, a semiconductor device includes a semiconductor substrate, a device portion disposed in the semiconductor substrate, and a junction terminal portion disposed in the semiconductor substrate and having an annular shape surrounding the device portion. The junction terminal portion includes first semiconductor regions of a first conductivity type and second semiconductor regions of a second conductivity type. The first semiconductor regions are adjacent to each other in a circumferential direction of the annular shape of the junction terminal portion, and have a width decreasing with progressing in a direction away from the device portion. The second semiconductor regions are disposed between the first semiconductor regions, and have a width increasing with progressing in the direction away from the device portion.

According to one embodiment, the semiconductor device includes a drift region, a first semiconductor region, a second semiconductor region, a main electrode, first gate electrodes and a second gate electrode. The first gate electrodes and the second gate electrode between a pair of first gate electrodes are provided in the drift region. The first semiconductor region is provided between the first gate electrodes and the second gate electrode. The first semiconductor region has a first side surface opposite to the one of the adjacent ones and a second side surface partially opposite to the second gate electrode. The second semiconductor region is selectively provided on the first semiconductor region. The main electrode has a portion directly adjacent to part of the second side surface and the second semiconductor region.

An image forming system includes an image forming apparatus and an upper device connected to the image forming apparatus. The image forming apparatus includes a first receiving unit for receiving a print mode including a cost priority mode; a first transmission unit for transmitting the print mode to the upper device; a second receiving unit for receiving a print instruction; a print control unit for printing the print data; a duplex print control unit for controlling a printing operation; and a fixing temperature control unit for controlling a fixing temperature. The upper device includes a first storage unit for storing a save setting; a third receiving unit for receiving image data; a second storage unit for storing the print mode; an arrangement print control unit for generating the print data; and a second transmission unit for transmitting the print instruction.

Image forming system and image forming apparatus configured for cost priority mode processing

According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second second conductivity type region is smaller in a quantity of second conductivity type impurities than the first second conductivity type region.

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, a fourth semiconductor region of the first conductivity type, a fifth semiconductor region of the second conductivity type, a first electrode, a second electrode, and a third electrode. The first electrode is provided together with the first region in a first direction, provided together with the third region in a second direction, and has an end portion of the first region side located nearer to the first semiconductor side than a boundary between the second region and the third region. The second electrode is provided between the first electrode and the first region and is in electrical continuity with the fourth region. The third electrode contacts with the fourth region.

Growing community of inventors

Tokyo, Japan

Mitsuhiko Kitagawa