Sharp Kabushiki Kaisha Corporation

Mitsuhiko Fujio

Kunihiko Iizuka

Masayuki Miyamoto

Hirofumi Matsui

An encoding apparatus uses a vector quantization encoding method for encoding indexes of codewords, which supply a scalar quantized code of a maximum scalar product value of each code word in a code book, and its maximum scalar product value to a vector component of an input image inputted from an image sensor, so as to output the encoded indexes. A scalar product value calculating circuit in the encoding apparatus has scalar product value calculating sections, which are composed of an analog circuit having a code component capacitor corresponding to each code component, a differential amplifier and a feedback capacitor, corresponding to each codeword, and the scalar product values of the input vectors are calculated in parallel by the scalar product value calculating sections. In such a manner, when the analog calculation is made, the scale of the circuit can be decreased and the power consumption can be lowered. Therefore, unlike the case where the calculation is made after A/D conversion, it is possible to avoid a problem that the number of times of calculations and the power consumption are remarkably increased due to increases in the number of dimensions of the input vector and the number of gradations.

Encoding apparatus

An image compressing apparatus employs a mean-separated normalized vector quantization method according to which, with respect to vector components corresponding to input images inputted from image sensors via a plurality of lines, encodes and outputs a scalar-quantized code of a mean value, a scalar-quantized code of a maximum scalar product value with each code word in a code book, and an index of one of the code words which yields a maximum scalar product value. In this image compressing apparatus, when the maximum scalar product value is less than a predetermined threshold value, in accordance with judgement by a comparator circuit, an output selecting circuit stops outputting the codes of the maximum scalar product value and of the index, and outputs only the code of the mean value. Therefore, when the image is uniform with pixels varying little in their luminance levels in compression processing unit blocks, code data to be outputted are restricted so that only data of the mean value are outputted. Consequently, it is possible to restrain degradation of the image and to considerably reduce data amount.

Image compressing apparatus

In respective comparators, a plurality of input voltages are compared with a comparison voltage that has been swept, and only the binary output of a D flipflop corresponding to the comparator that has exceeded the comparison voltage earliest is allowed to have '1', while the outputs corresponding to the rest of the comparators have '0'. Therefore, it is possible to detect a maximum output by using the comparators of a normal CMOS construction and a binary-change detection means circuit constituted by logical circuits. Compared with the application of floating-gate MOS, this arrangement makes it possible to reduce costs, and also to easily carry out offset-voltage compensation for each comparator by using switched capacitors. As a result, in a maximum input detector which detects a maximum input from analog inputs through multiple channels by carrying out analog operations, it is possible to reduce costs, and also to improve detection precision.

Input detector

An inner product calculation device for calculating an inner product of a coefficient vector including at least one first element with a positive sign and at least one second element with a negative sign and an input vector including elements corresponding to a plurality of input voltages. The device includes: an amplifier having an input terminal and an output terminal; a first capacitor corresponding to the first element and having a capacitance in proportion to a value of the first element; a second capacitor corresponding to the second element, and having a capacitance in proportion to an absolute value of the second element; a third capacitor connected to one end of the first capacitor, one end of the second capacitor, and the input terminal of the amplifier; a voltage source applying, during a first period a corresponding one of the input voltages to the first capacitor and a reference voltage to the second capacitor and the third capacitor; and applying, during a second period following the first period, the reference voltage to the first capacitor, a corresponding one of the plurality of input voltages to the second capacitor, and an output voltage output from the output terminal of the amplifier to the third capacitor; and a switch for short-circuiting the input terminal of the amplifier and the output terminal of the amplifier during a third period.

Inner product calculation device

A winner-take-all circuit for judging a channel receiving an analog signal having the largest or smallest value among multiple channels upon input of analog signals. Each basic circuit includes a detecting unit for comparing an input voltage with a reference voltage, and a feedback current generating unit for outputting a feedback current that determines a judging range in response to an output voltage from the detecting unit. The winner-take-all circuit also includes a tenth transistor serving as a common transistor to all the basic circuits. The tenth transistor secures, even when an input voltage is small, a current that should flow through a sixth transistor serially connected to the seventh transistor that determines an amount of a feedback current from the feedback current generating circuit. As a result, even when there are fewer k channels receiving input voltages having the highest level and slightly lower ones compared with all the n channels, a feedback current is secured in a sufficient amount to vary the reference voltage. In addition, the winner-take-all circuit of the present invention comprises analog circuits, thereby making the structure simpler compared with a counterpart that processes digital signals.

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Iizuka, Japan

Mitsuhiko Fujio