Fujitsu Corporation

Mitsuharu Sakakibara

Motoko Tanishima

Naoto Emi

Tomoharu Sohma

Junko Okawara

A non-volatile semiconductor memory device includes a memory cell array and an operation control circuit. The memory cell array includes a plurality of non-volatile memory cells that are electrically rewritable. The operation control circuit controls an operation of the memory cell array in accordance with an external instruction. The operation control circuit includes a flag circuit and an erase prohibition circuit. The flag circuit is set when erase incompletion is detected from any of the memory cells by an erase verify operation of the memory cell array. The erase prohibition circuit prohibits an erase operation to the memory cell array irrespective of the external instruction when the flag circuit is in a reset state.

Non-volatile semiconductor memory device, erase method for same, and test method for same

A memory circuit has a regular memory cell array; a redundant memory cell array that can replace a failed portion in the regular memory cell array; a redundant replacement memory for storing data on the failed portion in the regular memory cell array; and a pre-charge circuit disposed in the regular memory cell array, depending on the data on the failed portion, the failed portion in the regular memory cell array is replaced with the redundant memory cell array, whilst a pre-charge path is closed which leads to the pre-charge circuit corresponding to the failed portion. This enables a common redundant replacement memory to effect a relief of the failed portion and shutoff of the pre-charge current to the failed portion.

Growing community of inventors

Kawasaki, Japan

Mitsuharu Sakakibara