Mitsubishi Denki Kabushiki Kaisha

Mitsugu Satou

Shunichi Iwata

Toyohiko Yoshida

Hiroyuki Kondo

Masayuki Hata

Yukari Takata

Katsunori Sawai

Itsuko Kinoshita

Yuki Arima

A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit outputs the same value as that of the internal signal from each of external terminals. In the case where the internal signal does not need to be monitored, e.g., in the same manner as ordinary user's use, the output control circuit outputs an invariable value from each of the external terminals. Thus, in the case where the internal signal does not need to be monitored, the invariable value is outputted. Consequently, power consumption can be suppressed.

Single chip integrated circuit with external bus interface

A central processing unit (CPU) having a built-in dynamic random-access memory (DRAM) with exclusive access to the DRAM when the CPU performs an interlock access to the DRAM. A memory controller prevents the DRAM from being externally accessed while the CPU is performing the interlock access. When the memory controller receives an external request for accessing the DRAM during a time when the CPU is performing an interlock access to the DRAM, the memory controller outputs a response signal indicating that external access to the DRAM is excluded or inhibited. The request signal can be a hold request signal for requesting a bus right or can be a chip select signal. The response signal can be a hold acknowledge signal or a data complete signal. The memory controller can be switched to and from first and second lock modes, where hold request and hold acknowledge signals are used during the first lock mode and chip select and data complete signals are used in the second lock mode.

Computer system and semiconductor device on one chip including a memory

In a microprocesssor (101), a selector (7) is connected to a bus ID &lt;0:127&gt; through a write buffer (5) and a DRAM (27), a cache (28) and an IQ (8) are also connected to the bus ID &lt;0:127&gt;. The bus ID &lt;0:127&gt; and the microprocessor (101) are connected to the external memory (4) and the external bus master (41) with a data bus D &lt;0:15&gt; through a BIU (3). The microprocessor (101) is also connected to the external memory (4) and the external bus master (41) with an address bus (58) and control bus (57). The BIU (3) controls an access to a memory integrated in the microprocessor (101) and a memory externally connected thereto. With this configuration, the DRAM and the cache can be integrated together in the microprocessor which is externally connected to the bus master.

Bus interface unit in a microprocessor for facilitating internal and

When a CPU (1) writes '10' into a register (RG) provided in a controller (5), an AND gate (10) receives a CPU clock mask signal (CMS1) having the logic of '0' by one of its input terminals and accordingly cuts off the supply of a clock signal CLK to the CPU (1). Then, the CPU (1) is suspended, thereby reducing power consumption of the CPU (1). To return out of this state, a user has only to input an interrupt request to the controller (5) through a terminal (T1). Receiving the request, the controller (5) outputs the CPU clock mask signal (CMS1) having the logic of '1' to one of the input terminals of the AND gate (10) so as to supply the CPU (1) with the clock signal (CLK) again. Upon restarting the supply of the clock signal (CLK), the CPU (1) starts an operation to implement the interrupt request. With this configuration, an integrated circuit device including a control circuit for controlling operations of a processing circuit and a memory circuit with excellent operability can be provided.

Integrated circuit device with a memory that preserves its content

A data processor having a string operation instruction and a bit map operation instruction, and comprises a bus interface unit 157 which inputs/outputs data by the burst transfer function, and an integer operation unit 155 building-in a main ALU and a sub-ALU, wherein data is repeatedly transferred to/from an external memory via a data bus 102 in unit greater than a width of the data bus 102. Further, is can be accessed in a high speed by the block transfer in the burst mode to efficiently execute the above instructions, therefore the data string and bit map data can be executed quickly even when a low-cost slow memory system is connected thereto.

Data processor

A semiconductor integrated circuit includes an instruction execution controlling division which stops the execution of an instruction by stopping the renewal of a control signal in response to a signal representing that the instructing executing division is not prepared for receiving a control signal instructing the execution of the instruction or a signal representing that the decoded result of the instruction is invalid.

Semiconductor integrated circuit having a synchronous type memory

A clock generator which is provided with a circuit generating non-overlap clock from input clock, a frequency dividing circuit driven by the non-overlap clock and a latch disposed between the frequency dividing circuit and a clock driver, and whose critical pass being a cause of delay is shortened by sampling the frequency-divided output into the latch by the input clock and thereafter driving it by the clock driver, and a clock generator in which an internal clock at high speed in the internal clock logical value generating circuit is added with internal clock edge generating circuit required to operate at high speed and an output of initial stage of a buffer for inputting external clock is divided to supply to the internal clock edge generating circuit and to the other circuits, thereby capacity of the buffer required to operate at high speed in the circuit is decreased to reduce the delay of external clock.

Growing community of inventors

Tokyo, Japan

Mitsugu Satou