Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Mitsuaki Hayashi

Shuji Nakaya

Wataru Abe

Masakazu Kurata

Makoto Kojima

Yutaka Terada

Masanori Shirahama

Yasuhiro Agata

Akio Hirata

Toshiyuki Moriwaki

Tetsurou Toubou

Kenji Misumi

Nana Okamoto

An electronic equipment system includes a semiconductor integrated circuit having a nonvolatile memory storing information on a characteristic of the semiconductor integrated circuit; and a controller configured to control the semiconductor integrated circuit. The controller has a function of adjusting an access parameter to the semiconductor integrated circuit based on the information stored in the nonvolatile memory.

Electronic equipment system and semiconductor integrated circuit controller

In a conventional semiconductor memory device, a replica circuit configured by using a dummy bit line has been unable to charge the dummy bit line to a desired potential due to off leak current. Consequently, the time required for charging or discharging the dummy bit line differs from the desired time, and therefore, it has been unable to set optimum operation timing. To solve these problems, a semiconductor memory device of the present invention includes a dummy memory cell array in which source lines of dummy memory cells are charged simultaneously by a charge circuit configured similarly to a dummy bit line charge circuit, thus suppressing off leak current and performing appropriate timing generation.

Semiconductor memory device

A semiconductor memory cell is implemented in which the area of a row selection circuit is reduced and the effects of exposure, etching, and so on performed during manufacture are eliminated. The semiconductor memory device is provided with word line selection circuits connected with a row address signal line to select some desired word line according to an address input and dummy word line potential fixation circuits connected to word lines for dummy memory cells. As in the case of the word line selection circuits, the dummy word line potential fixation circuits each include a NAND gate NANDR(i) (i=&#x2212;1, 0, m+1, or m+2) and an inverter INVR(i) (i=&#x2212;1, 0, m+1, or m+2). The inputs of the dummy word line potential fixation circuits are connected with a row address signal line such that the word lines for the dummy memory cells are maintained in a non-selected state at all times. These make it possible to make the circuits which selectively drive all the word lines identical with each other in configuration, reduce the area of the row selection circuit, and eliminate the effects of exposure, etching, and so on during manufacture.

A semiconductor device is provided for outputting data read from a read only storage device. The semiconductor device includes a read only storage device including memory cells, an address signal line for transmitting an address signal to each read only storage device, and a switching device to which the address signal is inputted. The address signal indicates an address of memory cells storing data to be read. The switching device includes an address storage circuit, a bit storage circuit and a switching storage circuit. The address storage circuit stores address information of a defective memory cell of the read only storage devices and detects whether or not memory cells storing data selected by an address signal includes a defective memory cell. The bit storage circuit stores bit information indicating which bit of data stored in memory cells including a defective memory cell is defective, and outputs a controlling signal. The switching circuit inputs the controlling signal and data outputted from a read only storage device which is selected by an address signal and outputs the data from the read only storage device. The switching circuit inverts a defective bit of the data outputted from the read only storage device in response to receipt of the controlling signal from the bit storage circuit and outputs data whose defective bit is inverted instead of the data outputted from the read only storage device.

Semiconductor device for switching a defective memory cell bit of data to replacement data on the output data line

Subarrays, which constitute a memory cell array, each include a bit line driving transistor having a drain connected to a bit line, a source is connected to an interconnection having a power supply potential, and a gate is connected to a sub-bit line. The plurality of memory cells are each provided in such away that a gate is connected to a word line, a source is grounded, and whether a drain is connected to the sub-bit line or not is selected in correspondence to data to be stored. Transmission transistors each have a gate connected to the bit line, a source connected to a loading transistor section, and a drain connected to the sub-bit line.

A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit constituted by a plurality of transistors whose gates are connected to the bit lines, and a bit line precharge circuit which charges the selected bit lines for a fixed time period. As a result of adopting such a configuration, there is no need to provide a transmission gate, such as a column decoder, to a charging path between the read circuit and the bit lines, so that a low-power supply voltage operation can be effected without the influence of a substrate bias effect.

Semiconductor memory device having bit line precharge circuit controlled by address decoded signals

A semiconductor memory device is provided which has a hierarchical bit line structure and can perform a high-speed read operation even with a low voltage. A subarrayincludes a first MOS transistor PDfor charging a main bit line MBLand a second MOS transistor PSfor charging a sub-bit line SBL. The source electrode of the second MOS transistor PSis connected to a power source voltage, and the source electrode of the first MOS transistor PDis connected via a fourth MOS transistor PDto the power source voltage. Since there is not a resistance between the main bit line MBLand the sub-bit line SBL, which is present if a transistor is used to achieve conduction therebetween, discharging of the main bit line and charging of the sub-bit line can be performed with high speed.

A semiconductor device for outputting data read from a read only storage device, includes a plurality of read only storage devices, each including memory cells, a plurality of selecting signal lines for transmitting selecting signals to the read only storage devices for indicating a read only storage device storing data to be read, an address signal line for transmitting an address signal to the read only storage devices for indicating an address of memory cells storing data to be read and a switching device. The switching device has an address storage circuit for storing address information of a defective memory cell and detecting whether or not selected memory cells include a defective memory cell, a data storage circuit for storing replacement data for memory cells including a defective memory cell, and a switching circuit. The switching circuit inputs data from memory cells of a selected read only storage device and replacement data and outputs the data from the memory cells of the selected read only storage device and replacement data instead of data from the selected read only storage device which is stored in memory cells including a defective memory cell.

Semiconductor device for outputting data read from a read only storage device

An output end and an inverted output end of a latch circuit that is connected to an output buffer circuit are switched with each other, and thereby, the relationship between the data of '0' or '1' and the drain of a memory cell is connected or not connected to a bit line is changed. In addition, an input of a sense amplifier is fixed at the grounding potential by means of a test control signal, and thereby, positive logic is confirmed in the case where the output of the output buffer circuit is &#x201c;L,&#x201d; and negative logic is confirmed in the case where the output of the output buffer circuit is &#x201c;H.&#x201d;

Semiconductor memory with a data holding circuit having two output terminals

A dummy MOSFET including a dummy gate separates nMOSFETs included in adjacent memory cells arranged in the direction in which bit lines extend. This configuration reduces a stress applied from an STI to the channel regions of the nMOSFETs. Accordingly, decrease of drive currents of the nMOSFETs is suppressed.

Semiconductor memory and semiconductor integrated circuit

In view of the transistor off leakage increasing with device miniaturization, the invention provides a semiconductor integrated circuit capable of high-speed readout by eliminating the need for a charge replenishing transistor formerly required to hold a bit line at the &ldquo;H&rdquo; level, and thereby speeding up readout of stored data that causes the bit line to transition to the &ldquo;L&rdquo; level. To achieve this, a high-potential source line and a low-potential source line are provided. Then, the source of a memory cell is selectively connected to either the high-potential source line and the low-potential source line. In the case of stored data that causes the bit line potential to be held at the &ldquo;H&rdquo; level during readout, the source of the memory cell is connected to the high-potential source line, while in the case of stored data that causes the bit line potential to drop to the &ldquo;L&rdquo; level during readout, the source of the memory cell is connected to the low-potential source line.

Mask programmable read only memory

The object of the present invention is directed to shorten a manufacturing TAT when changing a stored data of a mask ROM incorporated into a semiconductor integrated circuit device with multi-layered structure, and to improve a manufacturing yield. For example, when the semiconductor integrated circuit device comprising an interconnection layer with five layers are manufactured, when fabricating samples or prototypes where data to be written to the mask ROM is frequently changed, the manufacturing TAT is shortened by means of configuring a bit line as a fifth layer of metal interconnection layer of an uppermost layer, and an interlayer dielectric (ILD) layer just below it as a forming layer of a via hole for use in data writing. During the manufacture of mass-produced products after determining the ROM data, it is possible to decrease the number of layers for configuring the memory cell by means of forming the bit line by the first metal interconnection layer of a lowermost layer, and configuring the ILD layer just below it as a forming layer of the via hole for use in data writing, to improve the manufacturing yield by reducing manufacturing process steps of the memory cell.

Method of manufacturing semiconductor integrated circuit device

By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.

A semiconductor memory device capable of reading out data at a higher speed and occupying a decreased chip-area is provided. The device includes a bit line selection circuit including a plurality of first transistors for selecting a plurality of bit lines according to a plurality of column selection signals generated based on address signals, a bit line charging circuit including a plurality of second transistors for charging the plurality of bit lines, respectively, and a bit line grounding circuit including a plurality of third transistors for connecting the plurality of bit lines with a ground potential. This enables the decrease in a charging time during a bit line precharging operation and a discharging time during data reading-out operation. Further, by grounding adjacent bit lines that are not involved in a precharging or reading-out operation so that they have a ground potential, it is also possible to minimize bit line intervals without causing a malfunction due to an increase in capacitances between the bit lines.

On a semiconductor substrate surface, a drain diffusion layer, which is in common to two transistors that make up a memory cell pair, is formed and source diffusion layers, for each of the transistors, respectively, are formed so as to sandwich the drain diffusion layer from both sides, a bit line is formed from a lower wiring layer and is connected to the drain diffusion layer, a source line is formed from the uppermost wiring layer, and the writing of information is performed by making a contact hole exist or non-existent immediately below the source line arranged from the uppermost wiring layer, in other words, by connection or non-connection of the source diffusion layer with the source line. By this arrangement, the TAT can be shortened and, since the capacitance of the bit line is not increased, high-speed operation with a short precharge time and discharge time for the bit line can be realized and the consumption power can be lessened.

Growing community of inventors

Kyoto, Japan

Mitsuaki Hayashi