Micron Technology Incorporated

Mithun Kumar Ramasahayam

Jiewei Chen

Tomoko Ogura Iwasaki

Michael J Gossman

Jordan D Greenlee

June Lee

Nancy M Lomeli

Luyen Tien Vu

Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.

Dynamic latches above a three-dimensional non-volatile memory array

A system for manufacturing a memory device forms a memory array comprising a plurality of memory cells arranged in a plurality of memory strings along a plurality of memory array pillars and forms a logic layer disposed above the memory array, the logic layer comprising a plurality of latches arranged along a plurality of logic layer latch pillars, the plurality of latches to store a multi-bit data pattern representing a sequence of bits to be programmed to the plurality of memory cells of the memory array.

Creating dynamic latches above a three-dimensional non-volatile memory array

An electronic device that comprises bitlines and air gaps adjacent to an array region of an electronic device is disclosed. The bitlines comprise sloped sidewalls and a height of the air gaps is greater than a height of the bitlines. Additional electronic devices are disclosed, as are methods of forming an electronic device and related systems.

Electronic devices comprising air gaps adjacent to bitlines

A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings extend through the insulative tiers and the conductive tiers. Horizontally-elongated trenches are between immediately-laterally-adjacent of the memory blocks. Conductor material is in and extends elevationally along sidewalls of the trenches laterally-over the conductive tiers and the insulative tiers and directly electrically couples together conducting material of individual of the conductive tiers. The conductor material is exposed to oxidizing conditions to form an insulative oxide laterally-through the conductor material laterally-over individual of the insulative tiers to separate the conducting material of the individual conductive tiers from being directly electrically coupled together by the conductor material. Additional embodiments are disclosed.

Growing community of inventors

Merdian, ID, United States of America

Mithun Kumar Ramasahayam