Intel Corporation

Mitesh Goyal

Abhishek A Sharma

Gururaj Shamanna

Jagadeesh Chandra Salaka

Harishankar Sahu

Purna C Nayak

A clock gate circuit (CGC) is described that optimizes dynamic power of the CGC when clock is gated. The CGC helps in dynamic power reduction of clock network by offering lower clock pin capacitance and also by providing clock pin driver downsizing opportunities. Switching power, and hence, dynamic power is reduced when load on the input clock pin is reduced. Further, dynamic power of the clock network also reduces by downsizing the clock buffers, which drive the CGC clock pins.

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Bengaluru, India

Mitesh Goyal