International Business Machines Corporation

Mitesh A Agrawal

Krishnendu Mondal

Benedikt Geukes

Franco Motika

Gerard M Salem

Preetham M Lobo

John D Parker

Tobias Webel

Santosh Balasubramanian

Pradeep N Chatnahalli

Prasad Shivaram

Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Simultaneous scan chain initialization with disparate latches

Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.

Methods and systems for performing test and calibration of integrated sensors

Embodiments include methods, and computer system, and computer program products for performing system functional test on a chip having partial-good portions. Aspects include: initializing, by system functional test software, a service engine of the chip, performing, by service engine, system functional test, and completing system functional test of chip. The chip may include service engine, a service engine memory and one or more 'partial-good' portions. The initializing may include: loading system functional test software into the service engine memory, identifying each 'partial-good' portion of the chip, writing a &#x201c;partial-good&#x201d; parameter for each &#x201c;partial-good&#x201d; portion of the chip identified to service engine memory, and triggering execution of system functional test. Method may include: decoding system functional test software, retrieving &#x201c;partial-good&#x201d; parameters, initializing &#x201c;partial-good&#x201d; portions of chip, and performing system functional test on &#x201c;partial-good&#x201d; portions of chip. The chip may include is a processor chip that has one or more &#x201c;partial-good&#x201d; cores.

Performing system functional test on a chip having partial-good portions

Methods for allocating spare latch circuits to logic blocks in an integrated circuit design are provided. A method includes determining logic blocks in the design and determining and determining an allocation of spare latch circuits among the logic blocks based on respective attributes of the logic blocks. The method further include placing the spare latch circuits in the design in accordance with the determined allocation based on local clock buffers corresponding with the logic blocks.

Distributing spare latch circuits in integrated circuit designs

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Jalgaon, India

Mitesh A Agrawal