Cadence Design Systems, Inc.

Other

Mitchell W Hines

Chih-Chang Lin

Manish Pandey

Pinhong Chen

Qi Wang

Kei-Yong Khoo

Vivek Chickermane

Ankur Gupta

Patrick Gallagher

Sandeep Bhatia

Huan-Chih Tsai

Christina Chu

Steven Sharp

Chung-Fu Chang

Reuber Duarte

Yonghoa Chen

A fish calling device for attracting predatory fishes by mimicking all sensory characteristics of a prey including appearance, sound and smell is disclosed. The device is configured to spray water into a waterbody around the device in a circular or a semi-circular pattern, thereby mimicking the appearance of a group of bait fishes. The water is sprayed to create the sound of a bait fish trying to escape from the predatory fishes when sprayed onto the waterbody. A scent bag is attached to the sprayer for dispersing/dispensing a smell through the water sprayer thereby mimicking the smell of a bait fish. Thus the device activates three senses of the predatory fishes including sight, hearing and smell for attracting them while fishing/competition.

System and method for attracting fish using sensory characteristics

A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.

Power domain crossing interface analysis

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Method and mechanism for implementing electronic designs having power information specifications background

A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application which can verify the complex characteristics in the circuits to the accurate RTL model function, including FPGA, ROM Arrays, RAM circuits, and other custom integrated circuit designs.

Method and system for creating a boolean model of multi-path and multi-strength signals for verification

A method to produce an information structure in computer readable memory that specifies power source hierarchy information for an RTL circuit design that includes multiple function instances encoded in computer readable memory, comprising: providing associations within the memory between respective function instances of the RTL design and respective power domains so as to define respective primary power domains relative to the RTL design; specifying in the memory respective secondary power domains; and providing associations within the memory that are indicative of respective power source relationships between respective primary power domains and corresponding respective secondary power domains.

High level IC design with power specification and power source hierarchy

This invention relates to method and apparatus for verification of circuit designs containing memories. At a register transfer abstraction level, verification of a circuit design requires showing that the register transfer language (RTL) abstraction of the design is logically equivalent to the design implementation represented at the logic (e.g., gate and/or flip-flop) and/or the transistor (e.g. implementation verification) abstraction levels, as well as logic simulation of the design RTL embedded in a system-level test bench for verification at the system-abstraction level.

Method and apparatus for verification of memories at multiple abstraction levels

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San Jose, CA, United States of America

Mitchell W Hines