International Business Machines Corporation

Mitchell R DeHond

David S Wolpert

William C Leipold

Daniel Nelson Maynard

Leon Jacob Sigal

Michael S Gray

David C Reynolds

Brian Douglas Pfeifer

Reginald B Wilcox, Jr

Adam P Matheny

Robert Mahlon Averill, Iii

Michael Alexander Bowen

Bette L Bergman Reuter

Gerald Strevig, Iii

Paul Joseph Ledak

Amanda Christine Venton

Betty L Bergman Reuter

Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.

Hierarchical color decomposition of library cells with boundary-aware color selection

Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.

Cross-hierarchy antenna condition verification

Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Hierarchical color decomposition of process layers with shape and orientation requirements

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Physical design characterization system

A method for automatically laying out a circuit starting from a logic gate diagram, especially for a CMOS technology. The logic is divided into blocks having a maximum number of serially connected transistors. Then the transistors are ordered to maximize the number of contiguously connected transistors. The ordered transistors then have their remaining connections determined according to the type of logic gate they represent.

Automatic layout for cascode voltage switch logic

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Essex Junction, VT, United States of America

Mitchell R DeHond