Advanced Micro Devices Corporation

Intel Corporation

Real 3-d

Mitchell H Singer

Jonathan Lawrence Campbell

Yuping Shen

Manu Rastogi

John A Carey

Hans Fernlund

Derrick Trevor Owens

Yue Zhuo

Raymond E Debs

Systems, apparatuses, and methods for performing command buffer gang submission are disclosed. A system includes at least first and second processors and a memory. The first processor (e.g., CPU) generates a command buffer and stores the command buffer in the memory. A mechanism is implemented where a granularity of work provided to the second processor (e.g., GPU) is increased which, in turn, increases the opportunities for parallel work. In gang submission mode, the user-mode driver (UMD) specifies a set of multiple queues and command buffers to execute on those multiple queues, and that work is guaranteed to execute as a single unit from the GPU operating system scheduler point of view. Using gang submission, synchronization between command buffers executing on multiple queues in the same submit is safe. This opens up optimization opportunities for application use (explicit gang submission) and for internal driver use (implicit gang submission).

Gang scheduling for low-latency task synchronization

Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

Indirect chaining of command buffers

A frame pacing method, computer program product, and computing system are provided for graphics processing. A method and system for frame pacing adds a delay which evenly spaces out the display of the subsequent frames, and a measurement mechanism which measures and adjusts the delay as application workload changes in an evenly spaced manner.

Method and system for frame pacing

The invention, in one embodiment, is a method for performing direct memory access. The method includes arbitrating between a chained, low priority, direct memory access and a high priority, direct memory access, the arbitration occurring between two links in the chained, low priority, direct memory access.

Technique for performing DMA including arbitration between a chained low

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Orlando, FL, United States of America

Mitchell H Singer