Cadence Design Systems, Inc.

Quickturn Design Systems, Inc.

Mitchell Grant Poplack

Yuhei Hayashi

Beshara G Elmufdi

Viktor Salitrennik

Barton Quayle

William F Beausoleil

Mikhail Bershteyn

Xiaolei Guo

John A Maher

Charles R Berghorn

Justin Schmelzer

Sundar Rajan

Hitesh Gannu

Aruna Aluri

Simon Luigi Sabato

Peter Tannenbaum

Steven T Comfort

Tung-Sun Tung

Tai Su

Linwei Ding

Phung Truong

Ping-Sheng Tseng

Sharon Mutchnik

Tarik Hanai Omar

N James Tomassetti

Christian Wiencke

Gavin Zawalski

Mark Alton Sherred

Ramesh Mogili

Jerome Albert

Catalino Datan, Jr

Christopher Coffman

TheHung Luu

Chuck Berghorn

Viktor Salittrennik

Zaid Khan

Bhoumik Shah

James Tomassetti

A shared memory is provided between simulation processors and emulation processors within an emulation chip. The shared memory is configured to enable the simulation processors and the emulation processors to exchange simulation data and emulation data respectively with each other during simulation and emulation operations. The simulation processors and the emulation processors may update their respective simulation and emulation operations in response to the simulation data and the emulation data exchanged via the shared memory.

Embedded processor architecture with shared memory with design under test

An emulation processor may be configured to support emulating unknown binary logic based on non-arbitrariness of the unknown binary logic. For example, an unknown binary logic signal may take the finite binary values of 0 and 1. The circuitry in the emulation processor is configured to generate and propagate outputs based on the interactions of known input binary signals with the unknown input binary signals having non-arbitrary states. The emulation processor may support the both combinational and sequential operations associated with the unknown binary logic.

Emulation system supporting representation of four-state signals

Embodiments disclosed herein describe switching logic in board-level interconnects and in the system-level interconnects that may provide bitwise dynamic routing and switching between corresponding board-level and system-level components. At board-level, a switching ASIC may receive input data through a backplane from an emulation ASIC in a first logic board and route any bit of the input data to any of the emulation ASIC in a second logic board. At system-level, a switching logic board containing a set of switching ASICs may be associated with a logic cluster and may dynamically route data bits from the emulation ASICs in the logic cluster to emulation ASICs to other logic clusters of the emulation system and/or target systems. Additionally, the switching logic board may dynamically route bits from the other logic clusters to the associated logic cluster.

System interconnect architecture using dynamic bitwise switch and low-latency input/output

A trace subsystem of an emulation system may generate differential frame data based upon successive frames. If one compression mode, the trace subsystem may set a flag bit and store differential frame data if there is at least one non-zero bit in the differential frame data. If the differential frame data includes only zero bits, the trace subsystem may set the flag bit without storing the frame data. In another compression mode, the computer may further compress the differential data if the frame data includes one (one-hot) or two (two-hot) non-zero bits. The controller may set flag bits to indicate one of all-zeroes, one-hot, two-hot, and random data conditions (more than two non-zero bits). For one-hot or two-hot conditions, the controller may store bits indicating the positions of the non-zero bits. For random data conditions, the controller may store the entire differential frame.

Systems and methods for enhanced compression of trace data in an emulation system

A system may include a synchronization device and an emulation chip including a processor and a memory. The processor may evaluate, during a first cycle, at least one of a set of one or more execution instructions in the memory or evaluation primitives configured to emulate a circuit, and evaluate, during a second cycle, at least one of the set of one or more execution instructions or a set of configured logic primitives. The synchronization device may interpose a gap period interposed between the first cycle and the second cycle such that during the gap period, the processor does not evaluate one or more instructions from the set of one or more execution instructions or re-evaluate primitives. The synchronization device may cause, during the first gap period, the emulation chip to perform refreshes on the memory of the emulation chip.

Systems and methods for intercycle gap refresh and backpressure management

Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated 'master TCI' and others are designated 'slave TCIs.' The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in &#x201c;infinite run&#x201d; and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.

Emulator synchronization subsystem with enhanced slave mode

Embodiments disclosed herein describe systems and methods for tuning phases of interface clocks of ASICs in an emulation system for a low latency channel and to avoid read errors. During a bring-up time (e.g., powering up) of the emulation system, one or more training processors may execute a software application to iteratively tune the phases of the interface clocks such that data is written to the interface buffers prior to being read out. To mitigate the problem of higher latency, the training processors may execute software application to tune the clock phases such that there is a small time lag between the writes and reads. The training processors may set the time lag to account for factors such as memory setup and hold, clock skews, clock jitters, and the predicted margin required to account for future clock drift due to carrying operating conditions.

Architecture and methodology for tuning clock phases to minimize latency in a serial interface

Emulation system supporting computation of four-state combinational functions

A pseudorandom logic circuit may be embedded as a hardware within an emulation system, which may generate pseudorandom keephot instructions. A masking logic may mask out portions in each pseudorandom keephot instruction, which may change state elements during execution. A cluster of emulation processors may execute masked pseudorandom keephot instructions to consume power when not executing mission instructions. The cluster of emulation processors may run keephot cycles, during which the cluster of emulation processors may execute the pseudorandom keephot instructions causing the cluster of emulation processors to continue consuming a roughly constant amount of power, either at a same or different voltage level, but supposed outputs of the pseudorandom keephot instructions may have no impact upon inputs and outputs generated during mission cycles.

Pseudorandom keephot instructions to mitigate large load steps during hardware emulation

Methods and systems herein can efficiently interconnect processors through a custom grid (a data mesh) utilizing upper metal layer routing in a semiconductor die design to minimize latency. A computer-implemented method of routing interconnects on a semiconductor die includes receiving a set of non-default routes and associated routing rules; identifying a set of critical signals for feedthrough on the set of non-default routes; generating a connectivity matrix including a set of resulting routes, the resulting routes routing the set of critical signals through the set of non-default routes; generating a timing analysis of the connectivity matrix based on a set of latency requirements; responsive to determining that the timing analysis is not compliant with the latency requirements, generating a set of routing constraints; and updating the associated routing rules to include the set of routing constraints.

Tiled datamesh architecture

Embodiments described herein provide for an emulation system that supports efficiently generating outgoing messages to a test bench. The emulation system transmits the outgoing messages to the test bench various busses and interfaces. The compiled virtual logic writes the outgoing messages into memories of the emulation chips for queuing, and notification messages associated with the queued outgoing messages. A traffic processor transfers from memories to the test bench using buses and interfaces. The traffic processor reads a notification message from memory to identify the storage location with a corresponding queued outgoing message. The traffic processor then transmits DMA requests to I/O components (e.g., DMA engines) to instruct the I/O components to transfer the queued outgoing message to the host device.

Systems and methods for handling DPI messages outgoing from an emulator system

A SPI master may configure a set of hardware registers associated with a SPI client with a set of communication parameters. The SPI master may send a message to the SPI client. The SPI master may periodically ping the SPI client until the SPI master receives an acknowledgement message from the SPI client in response to the message from the SPI master. The SPI master may periodically ping the SPI client based upon the set of communication parameters configured by the SPI master in the set of hardware registers. The SPI master may receive the acknowledgement message from the SPI client. The SPI master may determine a status of a read operation or a write operation associated with the message based upon the acknowledgement message.

Systems and methods for communicating with clients with non-deterministic response delay over a communication interface

The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation devices. Multiple statically scheduled selection tables (UCSWs), one for each output lane of the switching ASIC, drive the selection and routing of bits from input slots of various input lanes to the output slots of the output lane.

Dynamic one-bit multiplexing switch for emulation interconnect

Using a framing protocol, an application specific integrated circuit (ASIC) in an emulation system may transmit a start-of-packet molecule to a serializer-deserializer (SerDes) interface of a switching ASIC in a gap cycle leading up to an emulation cycle such that the switching ASIC may start routing mission data through the SerDes interface during the emulation cycle. The ASIC may transmit an end-of-packet molecule at a first gap cycle to the SerDes interface of the switching ASIC such that the switching ASIC may stop routing data through the SerDes interface during the gap cycles. The start-of-packet molecule may include a start-of-packet word, a status word, cyclic redundancy check word, and an idle word. The end-of-packet molecule may include an end-of-packet word, a status word, a cyclic redundancy check word, and an idle word.

Framing protocol supporting low-latency serial interface in an emulation system

Emulation system supporting four-state for sequential logic circuits

Growing community of inventors

San Jose, CA, United States of America

Mitchell Grant Poplack