International Business Machines Corporation

Mitchell E Medford

Michael R Primm

Sharon L Sanders

Jeffrey B Cripe

Jorge E Lenta

Luis A Hernandez

Esmaeil Tashakori

Nathan K Fritze

James W Cleary

Frederick C Stanley

Carolyn L Lay

A method and system for providing access to a protected partition of a direct access storage device in a data processing system which includes a direct access storage device, an adapter that commands I/O of the storage device and also contains a protection mechanism that restricts access to a memory partition on the storage device, an adapter device driver for controlling the adapter, and a system block device driver for transferring I/O commands to the system partition from the operating system to the adapter device driver. The method comprises the steps of receiving a request to perform a read or write to a protected memory partition, generating a command data block directing the storage device to perform the read or write, and generating a passthru command containing the command data block that directs the adapter to send the command data block without enforcing the protection of the memory partition. The method continues by sending the passthru command to the adapter which then passes the command data block on to the storage device to be executed without enforcing the memory partition protection.

Method and system for providing access to a protected partition of a

Protected system partition read/write access on a SCSI controlled DASD

An information handling network includes a plurality of information processing systems having a pretermit system configuration operating under the control of a corresponding number of operating systems where during a initial microcode load (IML) period prior to loading the operating systems a change in the system configuration is detected based on the predetermined system configuration. Upon detecting the change, a communication adaptor device is activated for communicating certain configuration information over the network before loading the operating system.

Apparatus for communicating a change in system configuration in an

A method and system for a graphical hardware description and testing interface is provided for use in conjunction with a data processing system. A polling system is provided for determining the configuration of the data processing system, including identification of the components. A graphic display is coupled to the polling system and utilized to display a graphic depiction of the data processing system, including any components. This graphic depiction is displayed in response to a determination of the configuration of the data processing system. The graphical hardware description and testing interface also includes a testing program for selectively testing a particular component to determine whether the component is defective. Also included is a display control circuit coupled to the graphic display. This display control circuit is utilized to selectively alter the graphic depiction of the data processing system, including any components, in response to the testing of the component.

Graphical system descriptor method and system

This invention relates to a personal computer having enhanced memory access capabilities, a memory element enabling such enhancement, and a method of operation of a personal computer. The invention contemplates that enhanced capabilities will be attained by enabling a choice between error detection technologies used.

Personal computer wherein ECC and partly error checking can be

This invention relates to personal computers having the capability for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate system controller; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of an error signal generated by an alternate system controller mounted in the connector and indicative of the failure of the alternate system controller. In response to detection of the error signal, the bus interface controller transfers control of the local processor bus from the alternate system controller to the microprocessor.

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Delray Beach, FL, United States of America

Mitchell E Medford