Arm Limited

Mitchell Bryan Hayenga

Curtis Glenn Dunham

Dam Sunwoo

Ali Ghassan Saidi

Christopher Daniel Emmons

Geoffrey Wyman Blake

An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

Indexing entries of a storage structure shared between multiple threads

A data processing apparatus executes a stream of instructions. Memory access circuitry accesses a memory in response to control signals associated with a memory access instruction that is executed in the stream of instructions. Branch prediction circuitry predicts the outcome of branch instructions in the stream of instructions based on a branch prediction table. Processing circuitry performs a determination of whether out-of-order execution of memory access instructions is to be performed based on memory prediction data, and selectively enables out-of-order execution of the memory access instructions in dependence on the determination. The memory prediction data is stored in the branch prediction table.

Memory dependence prediction

A data processing systemincludes a translation lookaside bufferstoring mapping data entriesindicative of virtual-to-physical address mappings for different regions of physical addresses. A hint generatorcoupled to the translation lookaside buffergenerates hint data in dependence upon the storage of mapping data entries within the translation lookaside buffer. The hint generatortracks the loading of mapping data entries and the eviction of mapping data entries from the translation lookaside buffer. The hint data is supplied to a memory controllerwhich controls how data corresponding to respective different regions of physical addresses is stored within a heterogeneous memory system, e.g. the power state of different portions of the memories storing different regions, which type of memory is used to store different regions.

Managing memory based on hint data generated from mapping data entries

A data processing apparatus has prefetch circuitry for prefetching cache lines of instructions into an instruction cache. A prefetch lookup table is provided for storing prefetch entries, with each entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the corresponding region from which processing circuitry accessed an instruction on a previous occasion. When the processing circuitry executes an instruction from a new region, the prefetch circuitry looks up the table, and if it stores a prefetch entry for the new region, then the at least one block identified by the corresponding entry is prefetched into the cache.

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Austin, TX, United States of America

Mitchell Bryan Hayenga