Intel Corporation

Mitchell Alexander Poplingher

Tse-Yu Yeh

Wenliang Chen

Carl C Scafidi

Monis Rahman

A method and apparatus for speculatively providing a branch target address as specified by an impending branch operation. In one embodiment, a branch prediction unit of the present invention is operable to pre-decode and pre-execute branch operations in a pipestage prior to a decoding stage and an execution stage of a pipelined processor. The branch operations of the present invention are performed via multiple instructions separately scheduled and executed, wherein a first instruction of a branch operation specifies a branch target, and a second instruction of a branch operation specifies when a branch of the branch operation is to occur. In an alternative embodiment of the present invention, the branch prediction unit is further operable to pre-fetch instructions from a memory hierarchy into a local instruction memory device in response to the branch prediction unit pre-decoding a first instruction of a branch operation.

Microprocessor having a branch predictor using speculative branch registers

A microprocessor is disclosed. The microprocessor includes a branch prediction table that has at least one branch entry. The at least one branch entry includes a prediction field to indicate whether a branch is predicted taken. The at least one branch entry also includes a history register that stores history information. Moreover, the branch prediction table includes a prediction update logic that updates the prediction field and the history register except when a branch is strongly predicted statically.

Optimized branch predictions for strongly predicted compiler branches

A pipelined microprocessor having a branch prediction unit implemented in an instruction pointer generation stage of the microprocessor. The branch prediction unit includes a memory device having at least a first entry configured to hold at least a part of a memory address of a pre-selected branch instruction and at least a part of a memory address of a branch target corresponding to the pre-selected branch instruction. The branch prediction unit compares an instruction pointer of an instruction to be executed with the memory address of the pre-selected branch instruction. In response to a match between the instruction pointer and the memory address of pre-selected branch instruction, the unit causes the microprocessor to fetch an instruction corresponding to the branch target. In one embodiment, the instruction pointer generation stage of the microprocessor is implemented as a first stage of the pipelined microprocessor. In addition, the branch prediction unit is compares the instruction pointer and the memory address of the pre-selected branch instruction during a single clock cycle in which the instruction pointer is generated.

Method and apparatus for performing early branch prediction in a microprocessor

A method of operation in a microprocessor is provided. A return address cache (RAC) is initialized. The RAC includes a portion to store predicted subroutine return addresses (PSRA) and first and second corresponding cache portions to store retired most recently updated (RMRU) ages of the PSRA and speculative most recently updated (SMRU) ages of the PSRA respectively. A PSRA is stored in a portion of the RAC corresponding to a first SMRU age and the SMRU ages are incremented responsive to prediction of a call instruction. A PSRA is read from a portion of the RAC corresponding to a second SMRU age and the SMRU ages are decremented responsive to prediction of a return instruction. Also a microprocessor that includes a return address cache (RAC) is provided. The RAC includes first and second tag portions to store retired most recently updated (RMRU) ages and speculative most recently updated (SMRU) ages respectively. The RAC also includes a data portion to store predicted subroutine addresses (PSRA). The RAC also includes a control logic to cause the RMRU ages to be copied onto corresponding SMRU ages responsive to detection of a branch misprediction.

Growing community of inventors

Campbell, CA, United States of America

Mitchell Alexander Poplingher