Vlsi Technology, Inc.

Mitchell A Stones

Nicholas Julian Richardson

Jeffery M Michelsen

CPU system performance is improved by reducing the time required to complete a DRAM access by microprocessors such as the 386DX, 386SX and 80286 by incorporating a programmable DRAM controller therewith which permits consecutive DRAM accesses to average N+0.5 processor wait states. The half wait state average is obtained by forcing the system CPU to measure wait states in processor clock time units which are twice the period of an independent clock in the DRAM controller which, in turn, triggers RAS and CAS assert and de-assert. RAS or CAS is thus able to assert 1/2 processor clock period earlier in one memory cycle relative to the last. Early assert time also provides for an early de-assert time so that data can be transferred to/from the DRAM more quickly than previously possible.

N+0.5 wait state programmable DRAM controller

A combination asynchronous cache system and automatic clock tuning device is disclosed in which the automatic clock tuning device includes at least a pulse generator, a counter, a unit delay tree, a comparing device, and a feedback path. A portion of the feedback path delivers a signal of interest off of the device chip in order that the signal experience the effect of the actual system impedance prior to being returned to the device chip for further manipulation of the signal. A major concept of the automatic clock tuning device is to enable a cache data/tag Write Enable (WE) signal to be clocked off of the falling edge of a delayed version of the System Clock (SCLK). This Delayed Clock (DCLK) signal is automatically delayed by a pre-selected amount each time that the rising edge of the WE signal occurs earlier than the rising edge of the SCLK signal. As long as the rising edge of the WE signal occurs slightly before or at the same time as the rising edge of the SCLK signal the CPU address/data hold time is successfully accomplished without adding superfluous wait states.

Combination asynchronous cache system and automatic clock tuning device

The amount of user configuration required for a programmable DRAM interface controller is minimized while assuring adherence to DRAM signal specifications and providing improved DRAM memory transfer performance using a novel intelligent programmable DRAM interface controller which allows programming of TRAS, TRP, TRCD, TCP, TCAS and TCST in units of the cpu clock/2 while obtaining TCSH and TRSH specifications without explicitly programming these parameters. THE TCSH specification is accomplished by holding CAS from deasserting until RAS has deasserted or until the RAS programmed low time has been met. The TRSH specification is accomplished by holding RAS asserted in all normal read or write accesses for at least one time unit after CAS has been asserted, which, in a majority of CPU/DRAM Systems, insures that the DRAM limitation TRSH is satisfied.

Growing community of inventors

Phoenix, AZ, United States of America

Mitchell A Stones