Intel Corporation

Mitchell A Kahn

Dennis M O'Connor

Byron R Gillespie

Jay S Heeb

Elliot D Garbus

Thomas M Johnson

Deif N Atallah

The state of cached data may be modified without performing a tag comparison. Each cache line includes at least one attribute bit and at least one state bit. A processor issues an instruction requesting modification of the state of all cache lines associated with an attribute specified by the instruction. Qualifying logic modifies the state of a cache line as a function of the attributes stored in the cache line and the attribute specified by the instruction.

Method and apparatus for quickly modifying cache state

The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected. As the structure of the protection mechanism does not require separate cycles in the processor, and simply monitors the memory bus for memory accesses, memory protection and detection can be performed with no additional overhead at the processor.

System for protecting memory accesses by comparing the upper and lower

System for protecting unauthorized memory accesses by comparing base

A microprocessor bus arbitration communications scheme for enhancing efficiency and performance of a multi-master bus system, typically within a computer system, including a central processing unit ('CPU') being a primary bus master, a bus arbiter and at least one alternative bus master coupled together by a bus. The CPU includes an internal memory element, a bus queue and bus control logic which collectively operate to generate a plurality of microprocessor bus arbitration signals to the bus arbiter. These microprocessor bus arbitration signals include a first bus arbitration signal indicating whether the CPU requires access to the bus and a second bus arbitration signal indicating that the CPU requires immediate access to the bus.

Multistate microprocessor bus arbitration signals

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San Jose, CA, United States of America

Mitchell A Kahn