Broadcom Corporation

Mitchell A Buznitsky

Brima Babatunde Ibrahim

Yuqian Cedric Wong

John S Walley

Angel Arturo Polo

Daniel C Bozich

Ahmadreza Rofougaran

Bojko F Marholev

Prasanna Desai

Hea Joung Kim

Siukai Mak

Langford M Wasada

Asif Grushkevich

Paul Anthony Lettieri

Theodore Trost

Masood Syed

Ming Yu Lin

Roy Tobin

Craig Stein

Nathan Le

Yingjie Zhou

Marholev Bojko

Ibrahim Brima

Desai Prasanna

Angel c/oBroadcom Corporation Polo

Joung Kim Hea

Mak Siukai

Certain aspects of a method and system for providing wireless communication may comprise encoding within a single chip, FM audio data received by a FM radio. The encoded received FM audio data may be translated within the single chip to a Bluetooth compatible format. The translated received FM audio data may be communicated to at least one off-chip Bluetooth enabled device via the Bluetooth radio via at least one of the following: a synchronous connection oriented (SCO) link, an extended SCO (eSCO) link, and an advanced audio distribution profile (A2DP) link. The received FM audio data may be communicated via a dedicated link that couples the FM radio to a PCM interface that handles the encoding.

Method and system for routing FM data to a bluetooth enabled device via a bluetooth link

A method and system sharing a Bluetooth processor for FM functions are provided. The single chip may comprise an integrated Bluetooth radio, an integrated FM radio, and processor system. A processor in the processor system may be utilized for Bluetooth and FM data processing and may time multiplex between the Bluetooth and FM data processing based on interrupt signals. The processor may operate in a low power mode based on a clock signal generated from a low power oscillator. When a Bluetooth interrupt signal is received, the processor may enable Bluetooth data processing that may be based on a Bluetooth clock signal. When an FM interrupt signal is received, the processor may enable FM data processing that may be based on an FM clock signal. When data processing is complete, the processor may return to the low power mode operation.

Method and system for sharing a Bluetooth processor for FM functions

A method and system for a single chip integrated Bluetooth and FM transceiver and baseband processor are provided. The single chip may comprise a Bluetooth radio, an FM radio, a processor system, and a peripheral transport unit (PTU). FM data may be received and/or transmitted via the FM radio and Bluetooth data may be received and/or transmitted via the Bluetooth radio. The FM radio may receive radio data system (RDS) data. The PTU may support digital and analog interfaces. A processor in the processor system may time-multiplex processing of FM data and processing of Bluetooth data. The single chip may operate in an FM-only, a Bluetooth-only, and an FM-Bluetooth mode. The single chip may reduce power consumption by disabling portions of the Bluetooth radio during FM-only mode and/or disabling analog circuitry when performing digital processing. Communication between Bluetooth and FM channels may be enabled via the single chip.

Method and system for a single chip integrated Bluetooth and FM transceiver and baseband processor

Determination and processing for fractional-N programming values. The present invention is operable to receive a clock signal (CLK) and to transform that CLK into a new CLK, when necessary, for use by various circuitries within a system. The present invention is operable to generate two different CLKs for use by a radio frequency (RF) circuitry and a baseband processing circuitry in certain embodiments. The present invention employs a measurement circuitry and to characterize a first CLK and uses a fractional-N synthesizer to perform any necessary processing to generate the one or more CLKs to the other CLKs within the system. The first CLK may be received from an external source or it may be generated internally; in either case, the present invention is able to modify the CLK into another CLK for use by other circuitries within the system or for use by another external device.

Determination and processing for fractional-N programming values

In one general aspect, a system may include a circuit board, a first integrated circuit attached to the circuit board, and a second integrated circuit attached to the circuit board being separate from the first integrated circuit and configured to operate in multiple power domains that include at least a core power domain and an I/O power domain and that is configured with a logic gate to receive and process external requests from the first integrated circuit and internal requests from the second integrated circuit for a common external resource.

Integrated circuit having a configurable logic gate

An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.

Reduced power consumption for embedded processor

An embedded ROM-based processor system including a processor, system memory, a programmable memory, a data selector and a patch controller. The system memory includes a read-only memory (ROM). The programmable memory stores patch information including patch code and one or more patch vectors. Each patch vector includes a break-out address from the ROM and a patch-in address to a corresponding location within the patch code. The data selector has an input coupled to the system memory and an output coupled to the processor. The patch controller is operative to compare an address provided by the processor with each break-out address to determine a breakout condition, and to control the selector to transfer the processor to a corresponding location within the patch code in response to a break-out condition. The programmable memory may be volatile memory, where the patch information is loaded from an external memory during initialization.

Patch memory system for a ROM-based processor

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Carlsbad, CA, United States of America

Mitchell A Buznitsky