Lsi Logic Corporation

Lsi Corporation

Mitchel E Lohr

Qwai Hoong Low

Steven L Haehn

Christopher D Macchietto

A packaged integrated circuit having a thermal pathway to exhaust heat from the integrated circuit. The integrated circuit is disposed on a package substrate, with an encapsulant disposed around the integrated circuit. A heat sink is disposed at least partially within the encapsulant, with at least a portion of one surface of the heat sink exposed outside of the encapsulant. The integrated circuit has an uppermost passivation layer, where the passivation layer is not electrically conductive, with a port disposed in the passivation layer. The port extends completely through the passivation layer to expose an underlying layer. A thermal pathway is disposed at least partially within the port, and makes thermal contact to both the underlying layer and the heat sink. The thermal transfer rate of the thermal pathway is greater than the thermal transfer rate either the passivation layer or the encapsulant.

Heat dissipation for integrated circuit

A method and a means for determining an I test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the I value of a test structure formed upon a die derived from the same lot of wafers as an integrated circuit. The method may further include setting the I test limit based upon the measured I value. In some embodiments, setting the I test limit may include correlating the I value of the test structure to calibration data. Accordingly, a means for conducting such a method may include one or more test structures formed upon a die and calibration data adapted to correlate a test structure I value to an I test limit of an integrated circuit. In some cases, the means for determining the I test limit may further include a means for increasing a substrate leakage current of the test structure.

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Windsor, CO, United States of America

Mitchel E Lohr