Qualcomm Incorporated

Mishel Matloubian

Abhijeet Paul

Periannan Chidambaram

Ravi Pramod Kumar Vedula

Hyunchul Jung

Yufei Wu

A complementary metal oxide semiconductor (CMOS) integrated humidity sensor with built-in heater is disclosed. In an aspect, a capacitive humidity sensor comprises a substrate and a plurality of unit humidity sensors disposed above the substrate. Each unit humidity sensor comprises a resistive heating structure disposed above the substrate, a plurality of capacitive humidity sensors disposed above the resistive heating structure and set apart from each other in a vertical direction, and a top surface at least a portion of which is water-permeable. Each capacitive humidity sensor comprises a pair of interdigitated vertical metal plates extending in a first direction, set apart from each other in a second direction orthogonal to the first direction, and separated from each other by a moisture-sensitive dielectric disposed between the pair of interdigitated vertical metal plates. At least one capacitive humidity sensor uses a different moisture-sensitive dielectric than another capacitive humidity sensor.

CMOS integrated humidity sensor with built-in heater

Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a conductive element on an isolation structure, a dielectric film, a first contact structure, wherein at least a portion of the dielectric film is disposed between the conductive element and the first contact structure, and a second contact structure disposed on and electrically coupled with the conductive element. The dielectric film is configured as a resistive element with the first contact structure and the second contact structure being terminals of the resistive element after a dielectric breakdown has occurred within the portion of the dielectric film. Also, the dielectric film is configured as an insulator of a capacitive element with the first contact structure and the second contact structure being terminals of the capacitive element in a case that no dielectric breakdown has occurred within the portion of the dielectric film.

Dielectric film based one-time programmable (OTP) memory cell

In an aspect, a device includes: a first patterned metal layer; a first dielectric layer disposed over the first patterned metal layer; a second patterned metal layer disposed over the first dielectric layer, wherein the first patterned metal layer, the first dielectric layer, and the second patterned metal layer form a first capacitor; a second moisture-sensitive dielectric layer disposed over the second patterned metal layer; and a third patterned metal layer disposed over the second moisture-sensitive dielectric layer, wherein the third patterned metal layer, the second moisture-sensitive dielectric layer, and the second patterned metal layer form a second capacitor that is moisture-sensitive, and the first patterned metal layer is further configured as a heating element to assist in removing moisture from the second moisture-sensitive dielectric layer of the second capacitor in response to provision of an electrical power to the first patterned metal layer.

Moisture sensor having integrated heating element

Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.

Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage

An integrated device that includes a substrate, a circuit region located over the substrate, a design keep out region located over the substrate, and a periphery structure located over the substrate. The design keep out region laterally surrounds the circuit region. The periphery structure includes a first plurality of interconnects that laterally surrounds the design keep out region. The periphery structure is configured to operate as an electrical seal ring and a mechanical crack stop.

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San Diego, CA, United States of America

Mishel Matloubian