Texas Instruments Corporation

Mishel Matloubian

Cheng-Eng D Chen

Ravishankar Sundaresan

Terence G Blake

Gordon P Pollack

Larry R Hite

Ted Houston

Daniel C Chen

The described embodiments of the present invention provide a method and structure for actively controlling the voltage applied to the channel of field effect transistors. In the described embodiments, a transistor connected to the channel region is fabricated. The channel transistor has opposite conductivity type to the transistor using the main channel region. The source of the channel transistor is connected to the channel and the drain of the channel transistor is connected to a reference voltage. The same gate is used to control the channel transistor and the main transistor. When a voltage which causes the main transistor to be on is applied, the channel transistor is off, thus allowing the channel to float and allowing higher drive current. On the other hand, when a voltage to turn off the main transistor is applied, the channel transistor is turned on, thus clamping the channel region to the reference voltage. This allows for consistent threshold voltage control of the main transistor. In a preferred embodiment, the channel of the main transistor is used as the source of the channel transistor and the gate of the main transistor extends onto the channel region of the channel transistor. The reference voltage is then connected to the drain region which is formed on the opposite side of the channel transistor channel region from the main transistor's channel.

Method of manufacturing semiconductor on insulator transistor with

Semiconductor on insulator transistor

A transistor and a method of making a transistor are disclosed, where a tunnel diode is formed to make connection between the source of the transistor and the body node underlying the gate. For the example of an n-channel transistor, a p+ region is formed by implant and diffusion under the n+ source region, the p+ region in contact on one end with the relatively lightly doped p-type body node. The relatively high dopant concentration of both the p+ region and the n+ source region creates a tunnel diode. The tunnel diode conducts with very low forward voltages, which causes the body node region to be substantially biased to the potential of the source region. Methods for forming the transistor are also disclosed, including the use of a source/drain anneal prior to p-type implant, or alternatively a second sidewall oxide filament, to preclude the boron from counterdoping the LDD extension at the source side. Both silicon-on-insulator and bulk embodiments are disclosed.

Silicon-on insulator transistor with internal body node to source node

A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

NMOS transistor having inversion layer source/drain contacts

An MOS transistor is disclosed which has a guard ring for prevention of source-to-drain conduction through the isolation oxide after exposure to ionizing radiation. In the described example of an n-channel transistor, a p+ region is formed at the edges of the source region in a self-aligned fashion relative to the gate electrode so as not to extend under the gate to contact the drain region. This p+ region forms a diode which retards source-drain conduction even if a channel is formed under the isolating field oxide where the gate electrode overlaps onto the field oxide. The structure may be silicided for improved series resistance. An example of the transistor formed in an SOI configuration is also disclosed.

MOS transistor with improved radiation hardness

A silicon-over-insulator transistor is provided having a semiconductor mesa (40) overlying a buried oxide (42). Insulating regions (50) are formed at the sides of the semiconductor mesa (40). An oxidizable layer (56) is formed over the mesa's insulating region (46). This oxidizable layer (56) is then anisotropically etched, resulting in oxidizable sidewalls (60). An optional foot (70) may be formed at the bottom edge of the oxidizable sidewalls (76). These oxidizable sidewalls (76) are then oxidized, resulting in a pure oxide sidewall (64). The gate (66) is then formed over the pure oxide sidewalls (64) and a gate oxide (62).

Thin oxide sidewall insulators for silicon-over-insulator transistors

An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).

Masking scheme for silicon dioxide mesa formation

The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Method of making silicon on insalator material using oxygen implantation

A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where the active devices will be formed) are covered by thick masking material 24, a high energy implantation step introduces additional doping into exposed silicon regions 14'. Before the mesa etch is performed to isolate the individual active device regions 32 a filament 28 is formed on the walls of the masking material 24 which covers the predetermined locations of the active device regions 32. The mesa etch is then performed using a chemistry which will be blocked not only by the original masking material 24 but also by the sidewall filaments 28. Thus, the doping level defined by implantation into regions 14' will extend into the sidewalls of the mesas 32 for a distance which is controlled not only by the lateral diffusion length of those dopants, but also by the thickness of the sidewall filament 28.

Growing community of inventors

Dallas, TX, United States of America

Mishel Matloubian