Sony Corporation

Sony Semiconductor Solutions Corporation

Misa Nakane

Satoshi Okada

Makiko Yamamoto

Takashi Yokokawa

Hiroyuki Kamata

Naoki Yoshimochi

Yuichi Hirayama

The present technology relates to a signal processing apparatus, a signal processing method, and a program capable of reducing the number of pins for transmitting and receiving data. The signal processing apparatus is provided with a signal transmission unit configured to perform classification for a signal to be transmitted and received between processing units that process an obtained signal, perform time division multiplexing for the signal classified into a group, and transmit the signal. The classification is performed depending on at least one feature of an update period, an update timing, and a tolerable transmission delay of the signal. Further, the signal belonging to the group is subjected to time division multiplexing in such a manner that the transmission is completed within the update period, the transmission is completed within a range of the tolerable delay, and the transmission is performed with a minimum number of pins. The present technology can be applied to a reception apparatus that receives and processes airwaves.

Signal processing apparatus and signal processing method

The present technique relates to a demodulation device, a demodulation method and a program capable of realizing a demodulation process at a rate equivalent to a case where I and Q channel signals are not inverted, even when the I and Q channel signals are inverted. A frequency correction unit establishes synchronization of a frequency and clock based on a signal from a frequency synchronization unit. A channel inversion detection unit of a frame synchronization unit detects presence or absence of inversion of I and Q channel signals, and supplies, as a detection result, a channel inversion detection result to the channel inversion control unit. The channel inversion control unit switches the I and Q channel signals if the inversion has occurred, based on the channel inversion detection result. This technique can be applied to a demodulation device.

Demodulation device, demodulation method and program

The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adderintegrates the product of an information word Dof six bits supplied from a cyclic shift circuitand the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum Dto a RAM. The RAMstores the sum D. Further, the RAMsuccessively reads out sums Dof 2 bits stored already therein and supplies the read out sums Das sums Dto an accumulatorthrough an interleaver. The accumulatorintegrates the sums Dand outputs a sum Dobtained as a result of the integration as a parity bit p of a codeword c through a selector. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.

Coding apparatus and coding method

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Tokyo, Japan

Misa Nakane