Micron Technology Incorporated

Lam Research Corporation

Round Rock Research, LLC

Western Digital (Fremont), Inc.

Mirzafer K Abatchev

Gurtej S Sandhu

Paul A Morgan

Baosuo Zhou

Shuang Meng

Luan C Tran

D Mark Durcan

William T Rericha

Krupakar Murali Subramanian

David H Wells

Ardavan Niroomand

Brian J Coppa

Zhiping Yin

John K Lee

Joseph Neil Greeley

Puneet Sharma

Sheron Honarkhah

Jingyi Bai

Ramakanth Alapati

Kevin G Donohoe

Robert G Veltrop

Rajinder Dhindsa

Andrew D Bailey, Iii

Eric A Hudson

Qian Fu

David K Hwang

Yufeng Hu

Zhongyan Wang

Shawn M Tanner

Brad J Howard

Alexei Marakhtanov

Ut Tran

Aaron R Wilson

Brian K McMillin

Tom A Kamp

Wei Gao

Aaron Eppler

Camelia Rusu

Yoko Yamaguchi

Yanfeng Chen

Alexei Marakhatanov

Yasushi Ishikawa

Tony Schrock

Krupaker Murali Subramanian

Raman Alapati

Jingyi (Jenny) Bai

Joseph Neil Greely

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

A method for processing a stack with a carbon based patterned mask is provided. The stack is placed in an etch chamber. A silicon oxide layer is deposited by atomic layer deposition over the carbon based patterned mask by providing a plurality of cycles, wherein each of the cycles of the plurality of cycles, comprises providing a silicon precursor deposition phase, comprising flowing an atomic layer deposition precursor gas into the etch chamber, where the atomic layer deposition precursor gas is deposited while plasmaless and stopping the flow of the atomic layer deposition precursor gas and providing an oxygen deposition phase, comprising flowing ozone gas into the etch chamber, wherein the ozone gas binds with the deposited precursor gas while plasmaless and stopping the flow of ozone gas into the etch chamber. Part of the silicon oxide layer is etched. The stack is removed from the etch chamber.

Silicon-based deposition for semiconductor processing

Methods and apparatuses for spacer profile control using atomic layer deposition (ALD) in multi-patterning processes are described herein. A silicon oxide spacer is deposited over a patterned core material and a target layer of a substrate in a multi-patterning scheme. A first thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a first oxidation condition that includes an oxidation time, a plasma power, and a substrate temperature. A second thickness of the silicon oxide spacer is deposited by multiple ALD cycles under a second oxidation condition, where the second oxidation condition is different than the first oxidation condition by one or more parameters. After etching the patterned core material, a resulting profile of the silicon oxide spacer is dependent at least in part on the first and second oxidation conditions.

Spacer profile control using atomic layer deposition in a multiple patterning process

Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.

Negative ion control for dielectric etch

A method for etching features in a stack comprising a patterned hardmask over a carbon based mask layer is provided. A pattern is transferred from the patterned hardmask to the carbon based mask layer, comprising providing a flow of a transfer gas comprising an oxygen containing component and at least one of SOor COS, forming the transfer gas into a plasma, providing a bias of greater than 10 volts, and stopping the flow of the transfer gas. A post treatment is provided, comprising providing a flow of a post treatment gas comprising at least one of He, Ar, N, H, or NH, wherein the flow is provided to maintain a processing pressure of between 50 mTorr and 500 mTorr inclusive, forming the post treatment gas into a plasma, providing a bias of greater than 20 volts, and stopping the flow of the post treatment gas.

Post etch treatment to prevent pattern collapse

Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.

Methods for integrated circuit fabrication with protective coating for planarization

Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n&#x2267;2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n&#x2212;1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n&#x2212;1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures

A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A fixed slotted valve plate having a first set of parallel slots therein is fixed in the conduit such that gasses withdrawn from the chamber into the conduit pass through the first set of parallel slots. A movable slotted valve plate having a second set of parallel slots therein is movable with respect to the fixed slotted valve plate so as to adjust pressure in the chamber.

Pressure control valve assembly of plasma processing chamber and rapid alternating process

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Fremont, CA, United States of America

Mirzafer K Abatchev