Westinghouse Electric Corporation

Other

Sundstrand Corporation

Mirza A Beg

Donal E Baker

David A Fox

Mark E Schumacher

A master clock generator for a variable speed constant frequency electric power system includes a frequency select circuit for selecting an external or internal frequency reference signal and a phase comparator for producing a phase error signal representative of the phase difference between the frequency reference signal and an output clock signal. The phase error signal is combined with a control signal to produce an adjusted phase error signal. This adjusted phase error signal is integrated and a voltage control oscillator is used to produce the output signal in response to the integrated adjusted phase error signal. The control signal introduces a desired phase error between the reference signal and the output signal. Clamping circuits are provided to limit the maximum and minimum magnitudes of the integrated adjusted phase error signal, thereby limiting the maximum and minimum frequencies of the output clock signal.

Master clock generator for a parallel variable speed constant frequency

A circuit is provided for detecting phase error between two signals by producing a phase error signal having a series of pulses wherein the widths of the pulses are representative of the phase error and producing a polarity signal representative of the polarity of the phase error. The phase error signal and polarity signal are used to produce a count representing the magnitude and polarity of the phase error for each of the pulses in the phase error signal. This count is converted to an analog signal which is compared to a pair of reference level signals to produce an output signal representative of the acceptability of the phase error corresponding to each of the pulses in the phase error signal.

Circuit and method for monitoring phase error modulation

An overcurrent trip circuit monitors the rate of rise of the current and the magnitude of the current in a power conductor and opens a circuit containing the power conductor when either the rate of rise of the current exceeds a first preselected limit value or the magnitude of the current exceeds a second preselected limit value. The inherent inductance in a metering shunt is used to produce a voltage signal that contains a component which is representative of the rate of change of current in a power conductor. This voltage signal is compared to a first reference signal to produce a trip signal when the voltage exceeds the first reference signal. In addition, the voltage signal is processed and the processed voltage signal is compared to a second reference signal to produce a second trip signal when the magnitude of the processed voltage signal exceeds the magnitude of the second reference signal. The power circuit is then opened in response to either of the first or second trip signals.

Overcurrent trip circuit

The widths of pulses in an incoming pulse train are monitored by successively measuring the duration of the pulses in the pulse train and enabling a timing device when the duration of any of the pulses is more than a preselected magnitude. The timing device is reset and restarted when the duration of any of the pulses is greater than the preselected magnitude. An output signal, indicative of an acceptable condition, is produced when the timing device indicates the expiration of a predetermined time delay. An output signal, indicative of a non-acceptable condition, is produced when the duration of a pulse in the incoming pulse train exceeds the preselected magnitude. This invention encompasses both the pulse width monitoring method and circuits which perform this method.

Circuit and method for monitoring voltage pulse widths

A method of selectively isolating faulty channels in a parallel electric power system having at least two controllable AC power sources includes the steps of producing a DC content signal representative of the magnitude of DC voltage in an AC output of one of the power sources and producing a differential current signal representative of differential DC current flowing in connected phases of the power sources. The DC content and differential current signals are combined to produce an error signal which is used to control the operation of the first power source, thereby reducing the magnitude of DC voltage in its output. When the error signal exceeds a predetermined threshold level, a trip signal can be produced and used to selectively isolate a failed channel in the power system. Following isolation of the channels, the differential current signal is disabled such that the error signal is only representative of the DC content signal for split channel operation.

Circuit and method for DC content protection of parallel VSCF power

A method for sensing real load unbalance in an electrical power system having at least two clock based power sources which are connected for parallel operation combines a real load difference current signal, proportional to the difference in real load currents in corresponding phases of the power sources, with a phase angle signal which is proportional to the phase difference between an external clock signal and an internal clock signal of one of the power sources, to produce an error signal. When this error signal exceeds a predetermined threshold level, a trip signal is produced to indicate that an excessive real load unbalance situation exists.

Real load unbalance protection system for parallel variable speed

A parallel power system includes at least two DC link variable speed constant frequency power sources each having a plurality of output phases connected to a common bus. The total real error current flowing in the output phases of each of the power sources is monitored and the relative phase angle of the Thevenin voltage of the power sources is controlled in response to the monitored total real error current to reduce the magnitude of this real error current. The reactive error current flowing in at least one of the output phases of each of the power sources is monitored and the relative magnitude of the Thevenin voltage of the power sources is controlled in response to the monitored reactive error current to reduce the magnitude of the reactive error current. For operation at no load, the phase angle control loop is sensitive to both real and reactive error currents.

DC link variable speed constant frequency power source paralleling

A solid state switching circuit is provided with a first power sharing circuit which incorporates resistive power dissipation elements so that the required dissipated power is shared between a main power transistor and the power sharing circuit. A second power sharing circuit is connected in parallel with a portion of the first power sharing circuit and operates to provide additional resistive power dissipation under certain switch voltage conditions. The use of this second power sharing circuit permits an increase in the required trip time of the main switching transistor or improves the reliability of the power transistors in the main circuit and the first power sharing circuit by lowering transistor stress during transient conditions.

Solid state current limited power controller for DC circuits

A clock control system for a multiple channel electric power system includes a master clock circuit and control circuitry in each parallel connected channel. The channel control circuits are intially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.

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Lima, OH, United States of America

Mirza A Beg