At+t Corp.

At&t Bell Laboratories

Miroslaw Guzinski

Ilyoung Kim

James Louis Lewandowski

Victor J Velasco

Shianling Wu

The testing of an n-bit encoder (14) and an n-bit decoder that collectively comprise a CODEC is performed by an apparatus including an n+1 bit counter (18) for generating a count, for generating an overflow signal once the counter has counted one beyond 2.sup.n -1. A digital comparator (26) is provided for comparing the count of the counter to a code generated by the encoder when the same is supplied with an input voltage. A logic circuit (24,25) is provided for sampling the counter to run freely for the purposes of testing the decoder and for enabling the counter to count each time the counter count equals the encoder code for purposes of testing the encoder.

Method and apparatus for testing a CODEC

An n-bit counter (18) (where n is an integer.gtoreq.1) may be tested by first reconfiguring the counter during a test mode to generate successive first and second half-counts when the counter is successively clocked. During the test mode, a logical equality comparator (70) compares the half-counts to each other. When the half-counts are unequal (signifying a counter fault), the counter is inhibited from further counting. In this way, the counter is advantageously frozen at the faulty value. When the counter is inhibited from counting, its carry bit (CO) no longer toggles. Thus, by examining the counter carry bit, an indication can be had whether the counter is operating properly during the test mode.

Method and apparatus for testing long counters

An N stage counter includes peripheral circuitry for testing the operability of the counter. The peripheral circuitry includes gating means coupled between certain stages of the counter for partitioning the counter into at least first and second counter sections during a testing mode. During the testing mode, the N counter stages are reset to an all zero condition and this resettability capability is detected. During the testing mode, the N counter stages are also set to a predetermined value and the settability of the counter stage to a non-zero condition is also detected. During one phase of the testing mode, the first section counts a predetermined number of clock cycles while all counts produced at the outputs of all the stages of the second section are totalled in a register means. During another phase of the testing mode, the second section counts a predetermined number of clock cycles while all the counts produced at the outputs of all the stages in the first section are totalled in the register means. Thus, during the one phase, the first section functions as a timer for the second section and during the second phase, the second section functions as a timer for the first section. The counts generated by the first and second sections are subsequently totalled and compared with a predetermined number to ascertain the operability of the counter.

Method and apparatus for testing large embedded counters

A device (12), such as an A/D converter for generating successive codes, each in accordance with the level of an input analog voltage, may be tested to determine if all codes have been generated by applying a voltage V.sub.t having an amplitude that varies between 0 and V volts. The variation in the voltage V.sub.t is such that when the device (12) is operating properly, it will generate all of its codes during a predetermined interval. Each code generated by the device (12) is compared by a comparator (18) to the count of an n-bit counter (20) whose count is initialized at zero. Each time the count of the counter (20) matches the code produced by the device (12), the counter is incremented. If the counter overflows (i.e., its count has exceeded 2.sup.n -1) within a prescribed interval, then the device (12) is said to be operating properly.

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Lawrenceville, NJ, United States of America

Miroslaw Guzinski