Hrl Laboratories, LLC

The Boeing Company

Hughes Electronics Corporation

J.a. Woollam Co.

Miroslav Micovic

Keisuke Shinohara

Andrea Corrion

Alexandros Margomenos

David F Brown

Paul B Hashimoto

Dean C Regan

Tahir Hussain

Shawn D Burnham

Ara K Kurdoghlian

Peter J Willadsen

Florian G Herrault

Hooman Kazemi

Rongming Chu

Wah S Wong

Keh-Chung Wang

Daniel P Docter

Colleen M Butler

Melanie Sachiko Yajima

Eric M Prophet

Joel C Wong

Ivan Milosavljevic

Yan Tang

Gary Peng

Hector L Bracamontes

David T Chang

Mehran Matloubian

David H Chow

Louis Luh

Peter W Deelman

Adam J Williams

Grant Andrew Ellis

JeongSun Moon

Bruce T Holden

Don Hitko

Mike Antcliffe

Blaine D Johs

Hasan Sharifi

Yakov Royter

Daniel Docter

Keisuke Shinihara

Ivan Alvarado-Rodriguez

Janna Ruth Duvall

Helen Hor Ka Fung

Ross L Bowen

A recursive metal-embedded chip assembly (R-MECA) process and method is described for heterogeneous integration of multiple die from diverse device technologies. The recursive aspect of this integration technology enables integration of increasingly-complex subsystems while bridging different scales for devices, interconnects and components. Additionally, the proposed concepts include high thermal management performance that is maintained through the multiple recursive levels of R-MECA, which is a key requirement for high-performance heterogeneous integration of digital, analog mixed signal and RF subsystems. At the wafer-scale, chips from diverse technologies and different thicknesses are initially embedded in a metal heat spreader surrounded by a mesh wafer host. An embodiment uses metal embedding on the backside of the chips as a key differentiator for high-density integration, and built-in thermal management. After die embedding, wafer-level front side interconnects are fabricated to interconnect the various chips and with each other. The wafer is then diced into individual metal-embedded chip assembly (MECA) modules, and forms the level one for multi-scale R-MECA integration. These modules are subsequently integrated into another wafer or board using the same integration approach recursively. Additional components such as discrete passive resistors, capacitors and inductors can be integrated at the second level, once the high-resolution, high-density integration has been performed at level zero. This recursive integration offers a practical solution to build very large scale integrated systems and subsystems.

Recursive metal embedded chip assembly

A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.

Monolithic integration of group III nitride epitaxial layers

Methods using chemical vapor deposition (CVD) of diamond deposited on a sacrificial material provide CVD diamond microchannel structures and 3-D interconnection structures of CVD diamond microfluidic channels. The sacrificial material is patterned to define locations and dimensions of the microchannels. The patterned sacrificial material is selectively removed from underneath the chemical vapor deposited (CVD) diamond to form the CVD diamond microchannels. The CVD diamond microchannels are integrated with electronic structures to provide an integral microfluidic cooling system to electronic devices.

Fabrication of microfluidic channels in diamond

Semiconductor devices, such as transistors, FETs and HEMTs having a non-linear gate foot region and non-linear channel width are disclosed as well as methods of making and using such devices and the operational benefits of the devices.

T-gate field effect transistor with non-linear channel layer and/or gate foot face

A method of mounting one or more semiconductor or microelectronic chips, which includes providing a carrier; temporarily adhering the one or more semiconductor or microelectronic chips to the carrier with active faces of the one or more chips facing towards the carrier; providing a package body with at least one chip-receiving opening therein and with at least one contact opening therein; temporarily adhering the package body to the carrier with the at least one opening in the package body accommodating at least a portion of the one or more chips; covering backsides of the one or more chips and filling empty spaces between the one or more chips and walls of the at least one opening in the package body with a metallic material; filling the at least one contact opening with the aforementioned metallic material; wirebonding contacts on the active faces of the one or more chips with contact surfaces in electrical communication with the metallic material in the at least one contact opening; and releasing package body with the one or more chips embedded in the metallic material from the carrier.

Surface mount package for semiconductor devices with embedded heat spreaders

A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

Stepped field plate wide bandgap field-effect transistor and method

There is provided an integrated RF subsystem including a chip substrate, a circuit patterned on a first surface of the chip substrate, a probe electrically integrated with the circuit on a first side of the chip substrate, a frame at a second side of the chip substrate defining a first cavity underneath the circuit.

Integrated RF subsystem

An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Wafer-level die to package and die to die interconnects suspended over integrated heat sinks

A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

Simultaneous controlled depth hot embossing and active side protection during packaging and assembly of wide bandgap devices

A method of forming an E-plane probe includes forming a plurality of monolithically integrated circuits (MICs) on a wafer, each MIC including a monolithic microwave integrated circuit (MMIC), and an E-plane probe coupled to the MMIC, mounting the wafer on an ultra-violet (UV) tape, cutting the wafer with a laser at a first power and a first linear cutting speed along vertical streets and then along horizontal streets to form separate substrates, cutting with the laser at a second power and a second linear cutting speed a rectangle or a portion of a rectangle from the separate substrates to form narrow substrate extensions on the substrates, and repeating this step for each rectangle or portion of a rectangle to be cut to form substrate extensions, and curing the UV tape, wherein the E-plane probes are on the narrow substrate extensions.

E-plane probe with stepped surface profile for high-frequency

A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.

Methods relating to a group III HFET with a graded barrier layer

Apparatus and methods are provided for heat removal and spreading from a field effect transistor (FET) including a substrate, a first source, a first gate, and a drain on the substrate, and a poly-diamond dielectric thermally coupled to the first gate wherein the poly-diamond dielectric facilitates heat removal from a top of the FET.

Near junction cooling for GaN devices

A self-aligned process for locating a stem of a T-shaped gate relative to source and drain contacts of a FET or HEMT. The gate stem is located asymmetrically in some embodiments and in such embodiments the stem of the T-shaped gate is located relative to drain and source contacts of the device by forming a plurality of sidewall spacers, with more sidewall spacers being formed on the drain side of the stem than are formed on the source side of the stem. Additionally the gate stem preferably has a high aspect ratio to improve the performance of the resulting FET or HEMT. Drain and source contacts are preferably formed of an n+ semiconductor material.

Methods of fabricating self-aligned FETS using multiple sidewall spacers

Growing community of inventors

Thousand Oaks, CA, United States of America

Miroslav Micovic