Infineon Technologies Ag

Apple Inc.

Intel Mobile Communications Gmbh

Mirko Sauermann

Jörg Gliese

Ulrich Hachmann

Ronalf Kramer

Matthias Heink

Wolfgang Raab

Mathias Richter

Alexander Schackow

Constantin Daniel Ciortescu

Vanja Rados

Cyprian Grassmann

Dominik Langen

Soeren Sonntag

The present disclosure describes a device including an initiator, a target, a communication bus coupling the initiator to the target over a channel, a functional circuit, and an error logger circuit. The functional circuit is coupled to the channel and can perform a function associated with a transaction request from the initiator to the target. The functional circuit can include an error detection circuit to detect an error associated with the function performed by the functional circuit and to generate an error indicator signal to indicate that the error has been detected. The error logger circuit can be coupled to the functional circuit, in which the error logger circuit is configured to receive the error indicator signal from the error detection circuit and store information about the error.

Error logger circuit

A data processing device is described with a memory and a first and a second data processing component. The first data processing component comprises a control memory comprising, for each memory region of a plurality of memory regions of the memory, an indication whether a data access to the memory region may be carried out by the first data processing component and a data access circuit configured to carry out a data access to a memory region of the plurality of memory regions if a data access to the memory region may be carried out by the first data processing component; and a setting circuit configured to set the indication for a memory region to indicate that a data access to the memory region may not be carried out by the first data processing component in response to the completion of a data access of the first data processing component to the memory region.

Data processing device and data processing arrangement for accelerating buffer synchronization

Logic basic cell and logic basic cell arrangement having a plurality of logic basic cells. A logic basic cell includes at least six data signal inputs, a first logic function block and a second logic function block, at least one logic function configuration input, a first multiplexer and a second multiplexer.

Logic basic cell and logic basic cell arrangement

Computer system for electronic data processing having programmable data transfer units used for transferring data from a first memory in which data is stored in a form of a multi-dimensional array to a second memory in such a way, that spatial or temporal locality for the transfer is established.

Computer system for data processing and method for the transfer of an array segment of an affine-indexed multi-dimensional array referenced in a loop nest from a first memory to a second memory

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Neubiberg, Germany

Mirko Sauermann