University of Virginia Patent Foundation

Intel Corporation

International Business Machines Corporation

Mircea R Stan

Kevin Skadron

Vivek K De

Ke Wang

Runjie Zhang

James W Tschanz

Siva G Narendra

Muhammad M Khellah

Yibin Ye

Alvar Antonio Dean

Stuart A Wolf

Elaheh Sadredini

Gholamreza Rahimi

Marzieh Lenjani

James E Jasmin

Luisa P Gonzalez Guerrero

Brett Meyer

David C Garrett

Jiwei Lu

Patricia Gonzalez

Adam C Cabe

Asynchronous stream generation and processing techniques are described that support implementation of an asynchronous stream mote in which one or more analog sensor signals are used to generate one or more asynchronous streams. On-device operations processing of the one or more asynchronous streams may be performed before transmission of the result(s) to other system components (e.g., peer motes or higher-level system components).

Asynchronous stream mote

Transient voltage noise, including resistive and reactive noise, causes timing errors at runtime. A heuristic framework, Walking Pads, is introduced to minimize transient voltage violations by optimizing power supply pad placement. It is shown that the steady-state optimal design point differs from the transient optimum, and further noise reduction can be achieved with transient optimization. The methodology significantly reduces voltage violations by balancing the average transient voltage noise of the four branches at each pad site. When pad placement is optimized using a representative stressmark, voltage violations are reduced 46-80% across 11 Parsec benchmarks with respect to the results from IR-drop-optimized pad placement. It is shown that the allocation of on-chip decoupling capacitance significantly influences the optimal locations of pads.

System for placement optimization of chip design for transient noise control and related methods thereof

A method of processing data in a memory can include accessing an array of memory cells located on a semiconductor memory die to provide a row of data including n bits, latching the n bits in one or more row buffer circuits adjacent to the array of memory cells on the semiconductor memory die to provide latched n bits operatively coupled to a column address selection circuit on the semiconductor memory die to provide a portion of the n latched bits as data output from the semiconductor memory die responsive to a memory read operation, and serially transferring the latched n bits in the row buffer circuit to an arithmetic logic unit (ALU) circuit located adjacent to the row buffer circuit on the semiconductor memory die.

Memory devices providing in situ computing using sequential transfer of row buffered data and related methods and circuits

A finite state machine circuit can include a plurality of rows of gain cell embedded Dynamic Random Access Memory (GC-eDRAM) cells that can be configured to store state information representing all N states expressed by a finite state machine circuit. A number of eDRAM switch cells can be electrically coupled to the plurality of rows of the GC-eDRAM cells, where the number of eDRAM switch cells can be arranged in an M&#xd7;M cross-bar array where M is less than N, and the number of eDRAM switch cells can be configured to provide interconnect for all transitions between the all N states expressed by the finite state machine circuit.

Methods, circuits, systems, and articles of manufacture for state machine interconnect architecture using embedded DRAM

A virtual force controlled collapse chip connection (C4) pad placement optimization frame-work for 2D power delivery grids is proposed. The present optimization framework regards power pads as mobile 'positive charged particles' and current resources as a 'negative charged back-ground.' The virtual electrostatic force is calculated from voltage gradients. This optimization framework optimizes pad locations by moving pads according to the virtual forces exerted on them by other pads and current sources in the system. Within this framework, three algorithms are proposed to meet various requirements of optimization quality and speed. These algorithms minimize resistive voltage drop (IR drop), the maximum current density, and power distribution network metal power dissipation at the same time.

System, method, and computer readable medium for walking pads: fast power- supply pad-placement optimization

The present invention proposes an electronic memory device comprising a memory line including a memory domain. The memory line may contain a number of memory domains and a number of fixed domains, wherein each memory domain stores a single binary bit value. A multiferroic element may be disposed proximate to each memory domain allowing the magnetization of the memory domain to be changed using a spin torque current, and ensuring the stability of the magnetization of the domain when it is not being written. The domain boundary between the memory domain and one of its adjacent fixed domains may thereby be moved. An antiferromagnetic element may be disposed proximate to each fixed domain to ensure the stability of the magnetization of these. The value of each memory domain may be read by applying a voltage to a magnetic tunnel junction comprising the memory domain and measuring the current flowing through it.

Magnetic random access memory device

A method of encoding data stored in a crossbar memory array, such as a nanowire crossbar memory array, to enable significant increases in memory size, modifies data words to have equal numbers of '1' bits and '0' bits, and stores the modified words together with information enabling the original data to be retrieved upon being read out from memory.

Method and system for encoding to eliminate parasitics in crossbar array memories

In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.

Representative majority voter for bus invert coding

Embodiments circuits provide a transistor body bias voltage so that the ratio of Ito Iis constant over a range of temperature, where Iis a transistor current when ON and Iis a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide Ito a current mirror that sources a current AIto a node, a nFET is biased to provide Ito a current mirror that sinks a current BIfrom the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AI=BI, where A and B are constants independent over a range of temperature. In this way, the ratio I/Iis maintained at B/A for some range of temperatures. Other embodiments are described and claimed.

Temperature dependent regulation of threshold voltage

A technique to individually adjust noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network includes identifying precharge nodes of the dynamic circuit that require a reduction of noise. The technique further includes identifying NMOS transistor drains connected to respective precharge nodes, and creating a pull-up network of PMOS transistors for the identified precharge nodes. After creating a pull-up network of PMOS transistors, the technique includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve noise immunity and performance of the dynamic circuit. After arranging the order of the PMOS transistors, the technique can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes.

Dynamic CMOS circuits with individually adjustable noise immunity

A multi-threshold flip-flop circuit having an outside feedback is disclosed. The multi-threshold flip-flop circuit comprises a master latch and a slave latch. Coupled between an output of the slave latch and an input of the master latch, a switchable feedback path is utilized to retain logical values of the slave latch during a sleep mode of the flip-flop circuit.

Multi-threshold flip-flop circuit having an outside feedback

A system of individually adjusting noise immunity of each input of a dynamic circuit including parallel or series-parallel pull-down network comprises identifying precharge nodes of the dynamic circuit requiring a reduction of noise. Then further identifying NMOS transistor drains connected to the respective precharge nodes, then creating a pull-up network of PMOS transistors for the precharge nodes, respectively. After creating a pull-up network of PMOS transistors, the system further includes arranging the order of the PMOS transistors corresponding to the respective precharge nodes to improve the noise immunity and performance of the dynamic circuit. After completing the arranging of the order of the PMOS transistors, the system can further include sizing the PMOS transistors to achieve the required reduction of noise for the precharge nodes, respectively.

Methods are provided for improving the efficiency of clock gating within low power clock trees. In a first aspect, a correlation level between a plurality of clock gating signals and their corresponding gates which gate a source clock is determined. The clock gating signals and their corresponding gates are combined into a single clock gating signal and a single corresponding gate if a preselected level of correlation exists therebetween. In a second aspect, an area overlap is determined for a plurality of sinks, and one of the gated drovers of the sinks is removed. The sinks of the removed gated driver then are connected to a remaining gated driver driven by a single clock gating signal and a single corresponding gate. In a third aspect, physically proximate sink clusters are rewired to generate a pure clock gating group within each sink cluster if rewiring the clusters increases wiring length by less than a predetermined amount. In a fourth aspect, a clock gating group is selected and the power dissipation is computed for all sinks within the selected group assuming all the sinks therein are wired without clock gating. The power dissipation also is computed assuming all the sinks therein are gated. If the power dissipation for all sinks within the selected group is reduced by individually wiring the sinks therein, the group is ungated. A computer program product also is provided having a computer readable medium with means for performing the first, second, third and/or fourth aspects of the invention.

Growing community of inventors

Charlottesville, VA, United States of America

Mircea R Stan