Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

Miranda Ma

Lei Pan

Zhen Tang

A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.

Multi-voltage input output device

A circuit includes first to third transistors. The first transistor includes a first terminal coupled to a first voltage, and a second terminal coupled to a connection. The second transistor includes a gate terminal coupled to the gate terminal of the first transistor, a first terminal coupled to a second voltage, and a second terminal coupled to the connection. The third transistor includes a first terminal coupled to the connection, a second terminal coupled to a node between the second terminals of the first and second transistors. The third transistor is controlled to be turned ON at a beginning of a first edge of a driving signal on the connection to pull a voltage of the driving signal on the first edge toward a threshold voltage, and be turned OFF in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.

Circuit

A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.

Failsafe circuit, layout, device, and method

A circuit includes a driver circuit configured to generate a driving signal having a first edge, an output circuit coupled to the driver circuit via a connection to receive the driving signal on the connection, and a compensation circuit coupled to the connection. The output circuit is configured to generate an output signal in response to the driving signal. A second edge of the output signal has a slew rate corresponding to a changing rate of a voltage of the driving signal on the first edge. The compensation circuit is configured to be enabled at a beginning of the first edge to pull the voltage of the driving signal on the first edge toward a threshold voltage. The compensation circuit is further configured to be disabled in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.

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Shanghai, China

Miranda Ma