Nec USA, Inc.

Miodrag Potkonjak

Sujit Dey

Jan Rabaey

Rabindra K Roy

Steven G Rothweiler

Lisa Guerra

A technique for optimizing the speed of sequential synchronous digital circuits. First, the bottlenecks that prevent retiming for shortening the delay period are identified and then conditions to eliminate the bottlenecks are derived. This involves identifying the subcircuits associated with the bottlenecks, satisfying a set of timing constraints on the subcircuits, and developing a new circuit that meets the timing constraints. The new circuit free of bottlenecks can generally be retimed by relocation of the forward slack latches to reduce the clock period.

Eliminating retiming bottlenecks to improve performance of synchronous

A method of high level circuit design synthesis using transformations based upon the addition of deflection operations reduces the interconnects and register requirements as well as the area requirements of a circuit design while preserving throughput without increasing the number of execution units needed. The method may also be applied to reduce the partial scan overhead for generating testable datapaths. The overall result of the transformations is to improve resource utilization and/or testability of circuits so designed.

High level circuit design synthesis using transformations

A method for performing high level synthesis of integrated circuits simultaneously considers testability and resource utilization. The method considers the relationship between hardware sharing, loops in the synthesized data path, and partial scan testing overhead. Hardware sharing is used to minimize the quantity of scan registers required to synthesize data paths with a minimal quantity of loops. A random walk based algorithm is used to break all control data flow graph (CDFG) loops with a minimal quantity of scan registers. Subsequent scheduling and assignment avoids the formation of loops in the data path by reusing the scan registers, while ensuring high resource utilization of the components of hardware costs: execution units, registers and interconnects. The partial scan overhead incurred is less than that of conventional gate level design partial scan techniques.

High level synthesis for partial scan testing

Non-scan design-for-testability methods for making register-transfer-level data path circuits testable include using EXU S-graph representation of the circuits. Loops in the EXU S-graph are made k-level controllable/observable to render the circuit testable without having to scan any flip-flops or break loops directly. Moreover, the resultant circuit is testable at-speed.

Non-scan design-for-testability of RT-level data paths

High level synthesis of datapaths has traditionally concentrated on synthesizing a specific implementation for a given computational problem. Methods to compose a reconfigurable BISR (built-in-self-repair) implementation with a minimum amount of area overhead are disclosed. Previously the BISR scope has been restricted to the substitution of operation modules with only those of the same type. Novel resource allocation, assignment and scheduling and transformation methods, primarily for ASIC designs, are described. These methods are based on the exploration of the design solution space accomplished by use of high level synthesis processes to find designs where resources of several different types can be backed up with the same unit.

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Plainsboro, NJ, United States of America

Miodrag Potkonjak