Skhynix Inc.

Yonsei University

Minyoung Im

Eui-Young Chung

Hongil Yoon

Jeongbin Kim

Kangwook Jo

Taehee You

A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

Technology mapping method of an FPGA

A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.

Look up table including magnetic element, FPGA including the look up table, and technology mapping method of the FPGA

Growing community of inventors

Seoul, South Korea

Minyoung Im