Gigadevice Semiconductor (beijing) Inc.

Gigadevice Semiconductor (shanghai) Inc.

Gigadevice Semiconductor (hefei) Inc.

Gigadevice Semiconductor Inc.

Shine Bright Technology Limited

Minyi Chen

A non-volatile memory includes a plurality of blocks and a controller. Each of the plurality of blocks includes a plurality of pages, and each of the plurality of pages includes a plurality of storage units. The controller is configured to perform: receiving an erase command for a target block of the plurality of blocks; executing a read operation on each page of the target block; and executing a first erase operation to apply word line voltages to the plurality of pages, where the word line voltages are determined by a read result of the read operation of each page. An operation method of a non-volatile memory and an electronic device are also provided.

Non-volatile memory and operation method thereof and electronic device

Provided are a flash memory and an operation method thereof. The flash memory includes a memory cell array, a controller and a register. The register stores read parameters that include a read voltage value and a read pass voltage value. The controller is configured to perform the read operation on a selected page according to the read parameters to read out the raw data stored in the selected page, determine whether the raw data includes an error bit, and in response to determining that the raw data includes the error bit, update the read parameters by decreasing the read voltage value and/or increasing the read pass voltage value.

Flash memory and operation method thereof

Disclosed are a nonvolatile memory and an operation method thereof. The nonvolatile memory includes a memory cell array and a controller. The controller is configured to: read out raw data from a plurality of memory cells in the memory cell array; correct the raw data by using error correction code (ECC) data to obtain corrected data; determine an address of a memory cell having a data loss error in the plurality of memory cells; and program the memory cell having the data loss error. After the ECC correction in the read operation, the data loss error is corrected by a program operation.

The present application provides a NAND flash memory, comprising: a control unit, which includes a signal receiving unit, a voltage boosted circuit and a flash array; and a power source supplying power to the control unit; wherein when the voltage boosted circuit receives an erase signal from the signal receiving unit, the voltage boosted circuit exerts a device erase pulse whose magnitude is larger than an initial voltage to blocks of the flash array to permanently erase data in the blocks; the blocks include power-on read blocks. By removing data from at least power-on read blocks, the present invention discloses a scheme for permanently destroying the NAND flash memory.

NAND flash memory and method for destroying information from the NAND flash memory

A NAND flash memory including a control unit which includes a signal receiving circuit and a flash array; the signal receiving circuit is used to receive a cache read command from an external NAND controller; the flash array includes at least one chip, each chip includes at least one plane, each plane includes a plurality of blocks, each block includes a plurality of pages; when a cache read command is received, it reads pages in a first block according to an address of the page until reaching the last page in the first block; when the last page in the first block is reached, an address of a next to-be-read page is generated according to an address of the last page in the first block to allow the cache read command to read the next to-be-read page.

Jump page cache read method in NAND flash memory and NAND flash memory

Provided are a programming method, programming apparatus and storage medium to reduce threshold voltage distribution in a non-volatile memory. The method includes performing program loops on a target page by sequentially using first programming voltages Vn; and when a predetermined condition is reached, proceeding to perform program loops on the target page by sequentially using second programming voltages Um until the target page is successfully programmed. Vn=V+(n&#x2212;1)&#xd7;d, where n denotes a program loop count of the first programming voltages, n is an integer greater than or equal to 1, and Vand dare all positive numbers. Um=Vn+(m&#x2212;1)&#xd7;d, where m denotes a program loop count of the second programming voltages, m is an integer greater than or equal to 2, and dis a positive number not equal to d

Programming method, programming apparatus and storage medium for non-volatile memory

Provided are an erasing method, erasing apparatus for memory cells and a storage medium to perform erase loops with a more appropriate erasing voltages. The method includes performing erase loops on a target erasing block by sequentially using first erasing voltages Vn; and when a predetermined condition is reached, proceeding to perform erase loops on the target erasing block by sequentially using second erasing voltages Um until the target erasing block is successfully erased. Vn=V1+(n&#x2212;1)&#xd7;d1, where n denotes erase loop counts of the first erasing voltages, n is an integer greater than or equal to 1, and V1 and d1 are positive numbers. Um=Vn+(m&#x2212;1)&#xd7;d2, where m denotes erase loop counts of the second erasing voltages, m is an integer greater than or equal to 2, and d2 is a positive number not equal to d1.

Erasing method and storage medium

The present application provides a NAND flash memory with wordline voltage compensate, including wordlines. Each wordline corresponds to a wordline voltage with a compensated temperature coefficient. The wordlines are divided into a plurality of groups, each group corresponds to a compensated temperature coefficient. Each wordline corresponds to a wordline address, and the groups of wordlines are divided by at least a border according to wordline addresses, or divided by zones having fixed number of wordlines.

NAND flash memory with worldline voltage compensation using compensated temperature coefficients

The present application provides a NAND flash memory and a method for indicating program status of wordline in a NAND flash memory, the NAND flash memory comprises: a wordline including a plurality of columns, the columns include NOP columns, which are used to store NOP bytes, one of the NOP bytes is programmed after the wordline is programmed for one time. The method includes: performing program operation to a wordline; and after the wordline is programmed for one time, programming one of NOP bytes; if all the NOP bytes are programmed, outputting a NOP status. The present application could effectively prevent the error occurs due to over-time programming the same wordline.

Method for indicating program state of wordline in NAND flash memory

The present application provides a status output method in NAND flash memory, including, setting ALE signal, CLE signal and WE#, signal wherein ALE and/or CLE signal is set to be 1 and WE# signal is set to be 1; when a falling edge of the RE# is detected, outputting LUN status signal of the NAND flash memory. Further, there is provided a NAND flash memory, including I/O signal pins, which includes an ALE signal pin, an CLE signal pin, a WE# signal pin, and a RE# signal pin; wherein when the ALE signal output by the ALE pin and/or CLE signal output by the CLE pin is 1, and WE# signal output by the WE# pin is 1, once a falling edge of the RE# is detected, the LUN status signal of the NAND flash memory is detected.

NAND flash memory and status output method in NAND flash memory

A NAND flash memory including a plurality of levels of cells and a plurality of bitlines. Each bitline corresponds to a plurality of program states, the program states include an Erase-state, a highest state and a plurality of middle states, wherein the bitline voltages of the middle states during programming are between the bitline voltage of the Erase-state and the bitline voltage of the highest state during programming, and the bitline voltages of the middle states during programming are different from each other. The bitline program voltages of middle states of a NAND flash memory are controlled, thus a higher initial programming voltage of wordlines can be set without causing over-programming on the middle states of the bitlines. Therefore, program time is saved, and the programming speed is increased to achieve a fast program function.

Growing community of inventors

San Jose, CA, United States of America

Minyi Chen