Samsung Electronics Co., Ltd.

Minyeong Song

Jaeduk Lee

Youngwoo Park

Jaehoon Jang

Younghwan Son

Jongwon Kim

Dohyun Lee

Chadong Yeo

A three-dimensional semiconductor memory device includes a horizontal semiconductor layer provided on a lower insulating layer. The horizontal semiconductor layer includes a cell array region and a connection region. An electrode structure is provided including electrodes. The electrodes are stacked on the horizontal semiconductor layer. The electrodes have a staircase structure on the connection region. A plurality of first vertical structures are provided on the cell array region to penetrate the electrode structure. A plurality of second vertical structures are provided on the connection region to penetrate the electrode structure and the horizontal semiconductor layer. Bottom surfaces of the second vertical structures are positioned at a level lower than a bottom surface of the horizontal semiconductor layer.

Three-dimensional semiconductor memory device

A three-dimensional (3D) semiconductor memory device includes an electrode structure including a plurality of cell electrodes vertically stacked on a substrate and extending in a first direction, lower and upper string selection electrodes sequentially stacked on the electrode structure, a first vertical structure penetrating the lower and upper string selection electrodes and the electrode structure, a second vertical structure spaced apart from the upper string selection electrode and penetrating the lower string selection electrode and the electrode structure, and a first bit line intersecting the electrode structure and extending in a second direction different from the first direction. The first bit line is connected in common to the first and second vertical structures. The second vertical structure does not extend through the upper string selection electrode.

Three-dimensional semiconductor memory device and method of operating the same

Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.

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Seoul, South Korea

Minyeong Song