Intel Corporation

Minxi Gao

Debendra Das Sharma

Fulvio Spagna

Michelle C Jen

Bruce A Tennant

Noam Dolev Geldbard

An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

Recalibration of PHY circuitry for the PCI express (PIPE) interface based on using a message bus interface

Recalibration of PHY circuitry for the PCI express (pipe) interface based on using a message bus interface

Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface

Growing community of inventors

Chandler, AZ, United States of America

Minxi Gao