Samsung Electronics Co., Ltd.

Minwoong Seo

Myunglae Chu

Hyunyong Jung

Seoksan Kim

Dongmo Im

Jaekyu Lee

Min-Jun Choi

SeungSik Kim

Jong-Yeon Lee

Jaeho Kim

JungChak Ahn

Taeyon Lee

Daehoon Kim

Uihui Kwon

Sungchul Kim

Sungyong Kim

Dongseok Cho

Jungchak Ahn

Jiyoun Song

Jongyeon Lee

Junan Lee

Minjun Choi

Daehee Bae

Sanggwon Lee

An image sensor includes a pixel array including a plurality of pixels; and processing circuitry, wherein each of the plurality of pixels includes: a photodiode; a floating diffusion node configured to integrate photocharge generated by the photodiode; a first capacitor configured to store charge corresponding to a voltage of the floating diffusion node which is reset; a first sampling transistor one terminal of which is connected to the second node, and another terminal of which is connected to the first capacitor, being configured to sample charge to the first capacitor; a second capacitor configured to store charge corresponding to the voltage of the floating diffusion node at which the photocharge has been integrated; and a second sampling transistor, one terminal of which is connected to the second node, and another terminal of which is connected to the second capacitor, being configured to sample charge to the second capacitor.

Image sensor

Provided is a pixel array including a plurality of pixels, each of which includes a photodiode configured to generate a photocharge in a frame including a plurality of unit frames, a floating diffusion node configured to receive the photocharge, a first storage capacitor configured to receive and store a first photocharge generated by the photodiode through the floating diffusion node during a first unit accumulation time period in each of the plurality of unit frames, and a second storage capacitor configured to receive and store a second photocharge generated by the photodiode through the floating diffusion node during a second unit accumulation time period in each of the plurality of unit frames.

Pixel array accumulating photocharges in each unit frame, and image sensor including the pixel array

An image sensor device including: a first digital pixel including a first photodetector and first memory cells to store a first digital signal corresponding to a first output from the first photodetector; and a second digital pixel including a second photodetector and second memory cells to store a second digital signal corresponding to a second output from the second photodetector, the second digital pixel is adjacent to one side of the first digital pixel, the first memory cells and the second memory cells are connected with a plurality of bit lines, the first memory cells are connected with a first word line and a third word line, the second memory cells are connected with a second word line and a fourth word line, the second word line is between the first and third word lines, and the third word line is between the second and fourth word lines.

Image sensor device

An image sensor device includes a pixel array, including digital pixels, and a pixel driver including a high-speed scanner that generates reset enable signals and signal enable signals. Each of the digital pixels includes a photo detector, a comparator, and a memory circuit. The high-speed scanner includes a first flip-flop and a second flip-flop. The first flip-flop receives a clock signal and a read trigger signal and outputs a first reset enable signal of the reset enable signals. The second flip-flop receives the clock signal and the first reset enable signal and outputs a first signal enable signal of the signal enable signals. The pixel array outputs a reset sampling value stored in the memory circuit in response to the first reset enable signal and outputs a signal sampling value stored in the memory circuit in response to the first signal enable signal.

An image sensor includes a first pixel outputting a first pixel signal, a second pixel outputting a second pixel signal, a ramp signal generator, and a comparator. The first pixel includes first transfer transistor, a first floating diffusion node, and a first gain control transistor. The second pixel includes a second transfer transistor and a second floating diffusion node. The comparator compares the first and second pixel signals. The first pixel operates in an HCG mode to output the first pixel signal as a first HCG pixel signal in a first period and operates in an LCG mode to output the second pixel signal as a first LCG pixel signal in a second period. A reset level of the second floating diffusion node of the second pixel is provided to the comparator through the column line in an interim reset period between the first period and the second period.

Image sensor, operating method of the same, and pixel including plurality of photodiodes

An image sensor includes a pixel array in which a plurality of pixels are arranged. Each of the plurality of pixels includes an organic photodiode of which a sensitivity is adjusted based on an external voltage, a silicon photodiode, first and second floating diffusion nodes, a conversion gain transistor, and a driving transistor. Charges generated by the silicon photodiode are accumulated in the first floating diffusion node. Charges generated by the organic photodiode are accumulated in the second floating diffusion node. One end of the conversion gain transistor is connected to the first floating diffusion node and the other end connected is connected to the second floating diffusion node. The driving transistor is configured to generate a pixel signal corresponding to a voltage of the first floating diffusion node.

An image sensing device including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to convert an analog signal into a digital signal is provided. The ADC includes a first circuit configured to receive the analog signal from a selected pixel among the plurality of pixels and generate a first output signal and a second circuit including a select transistor configured to apply a voltage to a floating node electrically connected to the select transistor based on the first output signal. The second circuit further includes a capacitor connected in parallel between a gate and a drain of the select transistor and an output circuit connected to the floating node and configured to output the digital signal based on the applied voltage to the floating node.

Amplifier, analog-to-digital converter including the same, image sensing device, and signal processing method thereof

An image sensor includes a pixel having an internal capacitor. Each of a plurality of pixels of the image sensor includes a photodetection circuit and an analog-to-digital converter (ADC). The photodetection circuit generates a detection signal. The ADC converts the detection signal using a ramp signal. The photodetection circuit includes a photodiode, a floating diffusion node and an overflow transistor. The floating diffusion node accumulates photocharges generated by the photodiode and includes a parasitic capacitor. The overflow transistor electrically connects the floating diffusion node to a first internal capacitor of the ADC.

Image sensor including pixel including internal capacitor

An image sensor includes a pixel including a photoelectric conversion device configured to convert sensed light into charges and a floating diffusion node configured to store charges provided from the photoelectric conversion device, a timing generator configured to generate a reset signal including, prior to a light-sensing period, a first reset signal pulse for enabling an erasing of charges stored in at least one of the photoelectric conversion device and the floating diffusion node, and generate a transfer signal including, subsequent to the light-sensing period, at least two transfer signal pulses, each transfer signal pulse enabling a moving of charges stored in the photoelectric conversion device to the floating diffusion node, and a readout circuit configured to generate output data by summing results of performing at least two samplings for the floating diffusion node based on the at least two transfer signal pulses.

Image sensor using multiple transfer, and operating method of the image sensor

An operating method of an image sensor, including performing a first sampling operation corresponding to first illumination in at least one pixel; performing a second sampling operation corresponding to second illumination in the at least one pixel; and outputting a first pixel voltage corresponding to the first sampling operation, or outputting a second pixel voltage corresponding to the second sampling operation, in the at least one pixel.

Image sensor, imaging device having the image sensor, and operating method thereof

The complementary metal oxide (CMOS) image sensor CIS includes a plurality of pixels arranged in a two-dimensional (2D) array and each including a photodiode, a plurality of analog-to-digital converters (ADCs) configured to perform auto exposure in units of the pixels, and a readout circuit configured to read pixel signals of the pixels, in rows. The plurality of pixels and the plurality of ADCs are the same in number and are connected in a one-to-one correspondence to each other. Each of the plurality of ADCs performs AE on a corresponding one of the pixels.

CMOS image sensor and auto exposure method performed in units of pixels in the same

Provided are a pixel array and an image sensor. The pixel array includes a plurality of pixels, which are arranged in a matrix form and which convert an optical signal into an electrical signal. The pixel array includes a first pixel arranged in a first row of the pixel array and a second pixel arranged in a second row of the pixel array, wherein each of the first pixel and the second pixel includes a first memory storing a digital reset value according to internal noise, the first memory of the first pixel stores m-bit data (where m is a natural number equal to or greater than 2), and the first memory of the second pixel stores n-bit data (where n is a natural number less than m).

Pixel array and image sensor including the same

A charge pump circuit includes a first pump unit and a second pump unit. The first pump unit includes a first capacitor and a first transistor, and generates a first node voltage by using a clock signal. The second pump unit includes a second capacitor, a second transistor, and a third transistor, and generates a negative output voltage by using the first node voltage. The clock signal and the first node voltage are each toggled between a low-level voltage and a high-level voltage. A magnitude of an absolute value of the negative output voltage is greater than a magnitude of an absolute value of the high-level voltage of the clock signal. A body of the third transistor is electrically isolated from a body of the second transistor.

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Hwaseong-si, South Korea

Minwoong Seo