Skhynix Inc.

Minsoon Hwang

Hee Jun Kim

Sang-Geun Bae

A controller configured to perform a training process of sampling data using multi-phase signals which are internally generated according to a data strobe signal, and compensating for a delay time of the data strobe signal using a control code which is generated according to the sampling result.

Controller and semiconductor system including a controller

A read clock generation circuit may include a multiplexer selecting one of divided clock signals in response to a selection signal and outputting the selected divided clock signal as a preliminary read clock signal, a detection circuit generating a detection signal for indicating detection timing of a divided clock signal having the fastest second edge after the first edge of a write clock signal, among the divided clock signals, based on a result of a comparison between the phases of the divided clock signals and the phase of the write clock signal, a counter generating the selection signal by counting the detection signal in response to the write clock signal, and a correction circuit outputting, as a read clock signal, a signal from which pulses corresponding to an invalid section have been removed, among the pulses of the preliminary read clock signal, in response to the detection signal.

Read clock generation circuit and data processing circuit including the same

Provided is a semiconductor controller that includes: an input buffer for comparing a data signal received from the outside with a reference voltage and storing the data signal; and a reference voltage control unit for generating the reference voltage corresponding to a protocol condition of the received data signal set between a first protocol condition and a second protocol condition and providing the reference voltage to the input buffer.

Electronic device and operating method thereof

A data output circuit includes: a voltage generation circuit configured to generate an operating voltage having a potential level higher than levels of a first power supply voltage and a second power supply voltage; a pre-driver circuit configured to generate pull-up code signals and pull-down code signals according to calibration code signals and the operating voltage; a data pre-driver circuit configured to generate and output internal data according to a data signal and the first power supply voltage; and a main driver circuit configured to generate output data according to the internal data and the second power supply voltage, wherein a driving strength of the main driver circuit is adjusted according to the pull-up code signals and the pull-down code signals.

Data output circuit

A data transmission system is provided. The data transmission system includes a plurality of data transmitters that respectively constitute a plurality of transmission lanes. Each of the plurality of data transmitters includes a serializer and an output signal storage circuit. The serializer coverts parallel input data into serial output data and outputs the serial output data. The output signal storage circuit stores the serial output data output from the serializer.

Data transmission systems having a plurality of transmission lanes and methods of testing transmission data in the data transmission systems

A memory system includes: a buffer memory device; and a memory controller configured to communicate data with the buffer memory device, wherein the memory controller includes: an input/output power voltage sensor configured to generate a first signal by sensing a change in input/output power voltage; and an impedance calibration circuit configured to perform an impedance calibration operation in response to the first signal.

Memory system having impedance calibration circuit

A memory system includes: a buffer memory device including a reference voltage pad; a memory controller including a controller ZQ pad; and a controller calibration resistor, wherein the reference voltage pad, the controller ZQ pad, and the controller calibration resistor are coupled to each other.

A memory system includes: a buffer memory device; and a memory controller including a data output driver configured to output data to the buffer memory device, wherein the data output driver includes: a pull-up switching unit coupled to an input/output power voltage, the pull-up switching unit including a PMOS transistor controlled by a data signal that varies according to the output data; a pull-up resistor unit including an NMOS transistor coupled to a DQ pad; a pull-down switching unit controlled by the data signal; and a pull-down resistor unit coupled to the pull-down switching unit.

Growing community of inventors

Gyeonggi-do, South Korea

Minsoon Hwang