Lg Display Co., Ltd.

Minsik Son

Juno Hur

Seungpyo Seo

Geunwoo Koh

Hoonseok Jang

Seungho Jang

SeRyong Park

A display apparatus includes a display panel including a gate line and a data line, a controller generating a source output enable signal determining an output timing of a data voltage output to the data line, and a data driver including a signal changer, generating a final source output enable signal by using the source output enable signal, and randomly changing the output timing of the data voltage for each gate line by using the final source output enable signal.

Display apparatus

A film element for driving a display device and a display device using the same are disclosed. The film element includes a film substrate including wirings and pads connected to the wirings, and an IC chip mounted on the film substrate to be connected to the wirings. The pads on the film substrate are grouped into a plurality of areas having different thermal correction amounts. Pads in a second area are closer to the IC chip than pads in a first area. A length of the first area is set to a length obtained by subtracting a first thermal correction amount from a first reference length. A length of the second area is set to a length obtained by subtracting a second thermal correction amount from a second reference length. The second thermal correction amount is smaller than the first thermal correction amount or has a negative value.

Film element for driving display device and display device using the same

A liquid crystal display is disclosed. The liquid crystal display includes a clock generator generating a first input clock signal and then a second input clock signal; a level shifter shifting the first and second input clock signals and generating clock signals whose voltages decrease stepwise from a gate high voltage, to a modulation voltage that is lower than the gate high voltage, to a gate low voltage that is lower than the modulation voltage; and a liquid crystal panel that includes data lines, gate lines intersecting the data lines, TFTs provided at intersections of the data lines and the gate lines, and a gate shift register sequentially supplying a gate pulse to the gate lines in response to the clock signals input from the level shifter.

Growing community of inventors

Paju-si, South Korea

Minsik Son