Broadcom Corporation

Minsheng Wang

Jungwoo Song

Xicheng Jiang

Anil Tammineedi

Nelson Ray Sollenberger

Yue Chen

Todd Lee Brooks

Taiyi Cheng

Iuri Mehr

Vinay Chandrasekhar

Josephus Van Engelen

Systems and methods are disclosed to provide automatic power control for a driver circuit. Embodiments disclosed herein enable a driver circuit to automatically decrease the gain of amplified input signals when output power exceeds a threshold. Further, embodiments disclosed herein enable a driver circuit to automatically increase the gain of amplified input signals when battery supply voltage drops to avoid unwanted output signal distortion. By using reference signals for battery power and amplified signal input, the amplifiers of the driver circuit can be automatically adjusted until an equilibrium is reached.

Distortion limiter and automatic power control for drivers

A Class-D amplifier arrangement is disclosed that implements an auxiliary feedback loop and a primary feedback loop. The auxiliary feedback loop operates upon an input signal when the Class-D amplifier arrangement is operating under a power-up condition and a power-down condition so that a modulated signal is confined within the auxiliary feedback loop during the power-up condition and the power-down condition. The confinement of the modulated signal within the auxiliary feedback loop during the power-up condition and the power-down condition diverts transient signals coupled onto the modulated signal from an output device. The primary feedback loop operates upon the input signal when the Class-D amplifier arrangement is operating under a normal condition so that the modulated signal is introduced to the output device during the normal condition.

Transient signal suppression for a class-D audio amplifier arrangement

Disclosed is a switching amplifier having an enhanced supply rejection. The switching amplifier comprises a digital modulator that provides a modulated signal. The switching amplifier further comprises a closed-loop analog driver that is coupled to the digital modulator. As disclosed, the closed-loop analog driver is configured to re-modulate a modulation signal that corresponds to the modulated signal. An output stage of the switching amplifier is driven by the re-modulated signal, thereby providing enhanced supply rejection. In one embodiment, the modulated signal is produced by a digital pulse-width modulator (PWM) circuit of a Class-D amplifier, and has a pulse rate substantially less than a clock rate of the digital PWM circuit. In one embodiment, the switching amplifier is implemented as an audio amplifier in a mobile communication device such as a cellular telephone.

Switching amplifier with enhanced supply rejection and related method

Disclosed is a closed-loop class-D amplifier circuit including a modulated reference signal generator that provides a modulated reference signal in a feed-forward path, where the reference signal is modulated corresponding to an input signal. The closed-loop class-D amplifier circuit further includes a comparator to generate a control signal based on a comparison of the modulated reference signal and a correction signal, which in turn is produced by filtering a combination of the input signal and a feedback signal. The closed-loop class-D amplifier circuit also includes a pulse generator to generate a pulse-width-modulated signal to drive an output stage of the closed-loop class-D amplifier based on the control signal.

Closed-loop class-D amplifier with modulated reference signal and related method

In a wireless device, a method and system for a baseband receiver interface including analog and digital components are provided. An analog or a digital interface may be selected for a I/Q data signal received from a front-end receiver. The analog interface may be a conventional RF or a VLIF interface. The I/Q data signal may be digitized when received from the analog interface and saturation detection may be used during digitization of the I/Q data signal. When the analog interface is the VLIF interface, a derotator may be used to remove the VLIF frequency. The derotator may be based on a CORDIC algorithm. The I/Q data signal may be converted from serial to parallel format when received from the digital interface. The received I/Q data signal may be decimated before transferred to a baseband processor.

Method and system for analog and digital RF receiver interface

Methods and systems for modulating an input electrical signal are disclosed and may comprise modulating input signals utilizing a digital Class-D modulator and generating a digital output signal that is proportional to the input signals. The digital Class-D modulator may be comprised of four stages. To avoid integrator saturation, the output of at least one integrator stage may be limited by utilizing limiters in integrator feedback loops. The digital Class-D modulator utilizes a pulse width modulation technique. For increased signal to noise ratio (SNR) at a desired output power, the magnitude of a triangular waveform oscillator voltage may be greater than the magnitude of an integrated input signal. The digital output signal may be fed back to an input of at least one of the four stages in the digital Class-D modulator. The triangular waveform oscillator frequency may be adjusted to match desired output frequency.

All digital Class-D modulator and its saturation protection techniques

In an audio processing device, a method and system for improved CODEC with polyringer are provided. An audio CODEC may comprise an audio ADC, an audio DAC, and a sidetone generator. Data from an external microphone may be processed by an audio ADC and may be sent to a processor that may be adapted to perform digital signal processing operations. The audio DAC may receive from the processor digital audio and polyphonic ringer data and may process the digital audio and polyphonic ringer data through separate digital filters and digital interpolators. The audio DAC may add the processed digital audio and polyphonic ringer data before analog conversion. The audio DAC may perform analog conversion by utilizing a delta-sigma modulator, a current-based DAC, and a switched-capacitor filter. The converted data may be filtered with an RC filter and may be utilized to drive an external speaker or earpiece.

Method and system for codec with polyringer

Methods for designing a filterless class-D amplifier and driver are described herein. In the exemplary embodiment, a feedback loop is used to stabilize the filterless class-D amplifier. A pulse width modulated (PWM) output signal is generated by adding a comparator input signal to a comparative signal, and comparing the sum to a peak voltage, which can be a peak value of the comparative signal. A limit of one PWM sample will be generated half per period of the comparative signal, resulting in lower dynamic switching noise and a decreased sensitivity to jitter noise than conventional filterless class-D amplifiers.

Filterless class-D speaker driver with less switching

A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that yields the product. The encoding is performed in a manner that allows the actual multiplication process to proceed quickly. X is copied into a variable Z. Z is then manipulated to form the coded version of the multiplier. The bits of the multiplier X are read two at a time, starting with the least significant two bits. If the bit pair XXis equal to 11, then 1 is added to Z. The process continues for successive non-overlapping pairs of bits, until the most significant three bits of X are reached. These last three bits are encoded using a table look-up process.

Method and system for high-speed multiplication

A data shuffler apparatus for shuffling input bits includes a plurality of bit shufflers each inputting corresponding two bits xand xof the input bits and outputting a vector {x', x&#x2032;} such that a number of 1's at bit x&#x2032; over time is within &#x2200;1 of a number of 1's at bit x&#x2032;. At least two 4-bit vector shufflers input the vectors {x&#x2032;, x&#x2032;}, and output 4-bit vectors, each 4-bit vector corresponding to a combination of corresponding two vectors {x&#x2032;, x&#x2032;} produced by the bit shufflers, such that the 4-bit vector shufflers operate on the vectors {x&#x2032;, x&#x2032;} in the same manner as the bit shufflers operate on the bits xand x. The current state of the bit shufflers is updated based on a next state of the 4-bit vector shufflers.

Hardware-efficient implementation of dynamic element matching in sigma-delta DAC's

A system and method is provided for stabilizing high order sigma delta modulators. The system includes an integrator having a limiter in the feedback path of the integrator. The integrator combines an input signal with a feedback signal generated by the limiter to produce an integrated output signal. The output signal is output to the next component of the sigma delta modulator. In addition, the output signal is fed back through the limiter. When an output signal received in the feedback path by the limiter exceeds the threshold value of the limiter, the limiter is activated and clamps the output signal to produce a limited signal. The limited signal is combined with the input signal to the integrator to produce the output signal.

System and method for stabilizing high order sigma delta modulators

An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to &#x3b1;* (maximum value of input signal), &#x3b1;&#x3e;1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0&#x3c;&#x3b1;&#x3c;2.0, more preferably 1.4&#x3c;&#x3b1;&#x3c;1.6. The filter has a transfer function of H(z)=2z&#x2212;z.

Error feedback structure for delta-sigma modulators with improved stability

A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

State-delayed technique and system to remove tones of dynamic element matching

Provided are a system and method for implementing a multirate analog finite impulse response (FIR) filter. A system of the present invention includes a modulator having a first adder and a quantizer. The first adder includes an output port, and the quantizer includes (i) an input port coupled to the first adder output port and (ii) a quantizer output port. A second adder is also included, having one input port coupled to the first adder output port and another input port coupled to the quantizer output port. Also included are at least two two-unit delays, a first of the two-unit delays having an input port coupled to an output port of the second adder, and an output port coupled to an input port of the second of the two-unit delays. An output port of the second two-unit delays is coupled to a first input port of the first adder.

Method and system for a multi-rate analog finite impulse response filter

A decimation system comprising a plurality, L, of cascaded Finite Impulse Response (FIR) decimation filters. Each decimation filter has a transfer function of the form H(z)=(1+z), where N is an integer. Each FIR decimation filter performs decimation by a common factor I. The cascaded FIR decimation filters together achieve a decimation result substantially identical to that of an N-order CIC filter (that is, a CIC filter having N integrator stages) that performs decimation by a factor I.

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Irvine, CA, United States of America

Minsheng Wang