Fujitsu Corporation

Spansion LLC.

Fujitsu Vlsi Limited

Sandisk Technologies Inc.

Minoru Yamashita

Takao Akaogi

Yasushi Kasa

Yasushige Ogawa

Tatsuya Kajita

Hisayoshi Watanabe

Kiyoshi Itano

Hiromi Kawashima

Nobuaki Takashina

Kazuhiro Kurihara

Kazunari Kido

Hiroaki Wada

Satoshi Takahashi

Shouichi Kawamura

Kyosuke Matsumoto

Yuki Fujita

Ryuji Yamashita

Masahiro Kano

Kei Kitamura

Shuzo Otsuka

Atsushi Hatakeyama

Yuichi Einaga

Norihiro Kamae

Biju Manuel

A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.

Double sense amp and fractional bit assignment in non-volatile memory structures

A method for programming a non-volatile memory structure, comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme of a plurality of memory cells, wherein the memory structure comprises: (1) a first memory array comprising a first population of memory cells and the associated peripheral circuitry disposed below the first population of cells, (2) a second memory array positioned above the first memory array and comprising a second population of memory cells and associated peripheral circuitry disposed above the second population of cells, and (3) a data bus tap electrically coupling the first and second memory arrays. Further, the method comprises: (1) storing input data in data latches associated with the first array and with the second array. Additionally, the method comprises converting the stored data using data conversion logic implemented by a data path circuit of the first and second arrays and rewriting the converted data to the latches.

Data conversion with data path circuits for use in double sense amp architecture with fractional bit assignment in non-volatile memory structures

A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.

Less-pessimistic static timing analysis for synchronous circuits

A semiconductor device in accordance with one embodiment of the invention can include a first data storage region including a non-volatile main data storage region. Additionally, the semiconductor device can include a second data storage region including a non-volatile reference region wherein an erasing operation and a writing operation are performed on both the first data storage region and the second data storage region. Moreover, the semiconductor device can also include a control unit coupled to the first and second data storage regions which determines a stress condition corresponding to the first data storage region based on a stress information related to the second data storage region.

Semiconductor device and method using stress information

A nonvolatile memory device that responds to a decrease in electric charge stored in memory cells attributed to the charge loss phenomenon occurring during program operation by adjusting the level of a program verify operation according to the degree of the charge loss so that the program operation can be performed with little (if any) interruption.

Nonvolatile storage device and control method thereof

The semiconductor device includes a memory cell array that includes memory cells for storing data and is managed on a sector basis, a memory that stores the information determining the activation status, a latch circuit that latches the activation information according to the information stored in the memory, and a circuit that latches the activation information according to the information stored in the memory in the latch circuit. The activation information according to the memory state of the memory is latched at the time of inputting a given command after activation, and it is thus possible to read the information stored in the memory and set the information in the latch circuit certainly.

Semiconductor device and control method of the same

A semiconductor device includes a first memory cell array that includes memory cells for storing data and is managed on a sector basis, a second memory cell array including memory cells storing sector protection information on the sector basis, and a control circuit checking the sector protection information stored in the second memory cell array whenever the sector to be programmed or erased is selected. Thus, the sector protection information in all the sectors does not have to be latched at the time of power on. The latch circuit equal in number to the sector does not have to be provided. It is thus possible to reduce the number of the circuits drastically and the chip area can be reduced.

Semiconductor memory device and control method having data protection feature

The semiconductor device of the present invention includes a column decoder (select and write circuit), which selects multiple pages that are not located adjacently to each other so as to simultaneously program multiple bits in the memory cells of the selected page, when the multiple bits are programmed in the multiple pages. The page is a selection unit and is composed of a given number of the memory cells located on a same word line. An unnecessary stress of programming is not applied to the memory cells that are not to be programmed, by increasing the distance between the memory cells to be programmed simultaneously.

Semiconductor device and programming method

The semiconductor device of the present invention includes at least one dummy cell of a programmed state proximately located to an edge of a reference cell array. Thus, the leak current does not flow when a data of the cell on the edge of the reference cell array is read out. The memory cell located around the center of the reference cell array has neighboring cells of the programmed state, and the leak current can be prevented when the data is read out from all the reference cells. Thus, the reference current can be supplied stably.

A nonvolatile memory has a plurality of memory cells, each of the memory cells having a first and a second source/drain areas, a control gate, and an insulating trap layer disposed between the control gate and a channel area lying between the first and the second source/drain areas. The trap layer includes a use bit area in proximity to the first source/drain area, for storing data depending on the presence or absence of electric charge to be trapped, and a non-use bit area in proximity to the second source/drain area, in which the electric charge is trapped while data is held in the use bit area. Preferably, in the state where erasing operation is completed, the non-use bit area is brought into a state where electric charge is trapped therein.

Nonvolatile memory having a trap layer

A semiconductor memory that prevents a decrease in margin at read time. A bit line in a floating state between a drain in a memory cell to be read and a charged bit line is charged for a certain period of time.

Non-volatile semiconductor memory that is based on a virtual ground method

A non-volatile semiconductor storage device provided with a boost circuit for setting, for at least a certain period of time, a source line selectively connected to a memory cell to a negative potential, when reading out data from the memory cell is disclosed.

Non-volatile semiconductor storage device and method of reading out data

In a nonvolatile semiconductor memory device, first and second dynamic reference cells are subjected to a same rewriting operation as performed to a memory cell. An average reference current is obtained from the first and second dynamic reference cells, and is compared with a current of data read from the memory cell so as to judge a level of the read data. In this configuration, the second dynamic reference cell is programmed according to a threshold value of the first dynamic reference cell.

Nonvolatile semiconductor memory device programming second dynamic reference cell according to threshold value of first dynamic reference cell

A semiconductor memory device has 2 word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2 (n>m) word lines among the 2 word lines, and a second unit for not selecting a block of 2 (m>k) word lines among the 2 word lines. The second unit does not select the block of 2 word lines, and selects a block of 2 word lines prepared outside the 2 word lines when any one of the 2 word lines among the 2 word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

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Kawasaki, Japan

Minoru Yamashita