Hitachi, Ltd.

Minoru Yamada

Keiichirou Nakanishi

Akira Masaki

Noboru Masuda

Masakazu Yamamoto

Moritoshi Yasunaga

Masayoshi Yagyu

Mitsuo Asai

Katsunari Shibata

Kenichi Ishibashi

Katuo Sugawara

Kuninori Imai

Kazumichi Yamamoto

Tatsuya Saitoh

Kazuo Sato

Akio Takahashi

Mitsuo Usami

Kazuya Takahashi

Takahiro Daikoku

Hideo Suzuki

Takehisa Hayashi

Hiroki Yamashita

Motoyo Wajima

Ryoichi Kajiwara

Fumiyuki Kobayashi

Satoru Ogihara

Yutaka Harada

Masatoshi Watanabe

Toshio Doi

Takashi Nishida

Takao Funamoto

Hirotoshi Tanaka

Kenji Nagai

Hiroichi Shinohara

Michio Asano

Masahide Tokuda

Tomohiko Shida

Katuaki Chiba

Hiroshi Wachi

Atsumi Kawata

Mitsuru Usui

Nobuhiro Taniguchi

Mituo Katou

Takeshi Matsuzaka

Yuzo Hirai

Yuko Isozaki

Mararu Osanai

Masaru Osani

An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

Information processing apparatus

A semiconductor integrated circuit device includes a plurality of integrated circuit chips and a large-sized integrated circuit element on which the plurality of integrated circuit chips are mounted. The large-sized integrated circuit element includes a logic circuit for electrically interconnecting the integrated circuit chips mounted on it. The logic circuit provided within the large-sized integrated circuit element includes a control circuit for controlling a connection relation between the integrated circuit chips mounted on the large-sized integrated circuit element. Further, the logic circuit includes buffer or latch circuits for relaying signals transmitted between the integrated circuit chips.

Semiconductor integrated circuit device and computer system using the

A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.

Serial to parallel data converting circuit

The logic gates are usually logically arranged in a first hierarchical structure in terms of a cluster of logical functions certain logic function elements are selected as to-be-processed function elements on the basis of the number of hardware components and a maximum allowable number of gates each hardware component can accommodate. Selected to-be-processed function elements in the first hierarchical structure are classified into at least two element groups based on connection strengths among the to-be-processed function elements and a maximum allowable number of pins and gates each hardware component can carry and accommodate, respectively. Using the classification result, the selected to-be-processed function elements in the first hierarchical structure are rearranged into a second hierarchical structure in terms of a cluster of logical functions in which all of the to-be-processed function elements are partitioned into the plurality of group elements so that each of the group elements corresponds to those of the logic function elements which are physically assignable to a different one of the hardware components.

Method of and apparatus for assigning logic gates to a plurality of

An information processing apparatus which includes an input layer, a hidden layer and an output layer, and performs a computation in terms of models of neurons. A forward network, having the input layer, the hidden layer and the output layer, executes a computation for externally input data to determine the values of outputs therefrom, and a backward network, having the output layer and the hidden layer, executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.

A semiconductor integrated circuit device has, in one embodiment, a pair of signal transmission lines formed over and insulated from a semiconductor substrate, a first circuit formed in the semiconductor substrate and electrically connected with one end of the pair of signal transmission lines for sending an electric signal, and a second circuit formed in the semiconductor substrate and electrically connected with the other end of the pair of signal transmission lines for receiving the electric signal propagating over the transmission line pair. A control resistance is electrically connected between the pair of transmission lines at the above-mentioned other end for controlling a delay time of the signal propagating over the pair of signal transmission lines between the opposite ends of the pair of signal transmission lines.

Semiconductor integrated circuit device having a signal transmission

This invention discloses an integrated circuit device including an integrated circuit chip having logic circuits formed therein and a wiring substrate for mounting thereon the integrated circuit chip. The wiring substrate has signal wirings for connecting mutually input terminals and output terminals of the integrated circuit chip. The integrated circuit device includes signal wirings for effecting connections of the input terminals and output terminals of the same integrated circuit chip inside the wiring substrate. The logic circuits inside the same integrated circuit chip are mutually connected by signal wirings formed inside the integrated circuit chip when a wiring length is small, and are mutually connected by signal wirings formed inside the wiring substrate when the wiring length is great.

Integrated circuit device having an ic chip mounted on the wiring

An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Information processing system

A thick film and thin film composite wiring substrate for mounting integrated circuit chips thereon, comprising a thin film substrate including a signal wiring layer therein, a thick film substrate laminated together with the thin film substrate, and at least a part of signal wiring being formed as a signal wiring layer included in the thick film substrate.

Thick film and thin film composite substrate and electronic circuit

The present invention relates to a chip carrier, on which LSI chips are mounted and a chip carrier is disclosed, in which a region where power source throughholes are arranged and a region where signal throughholes are arranged are separated from each other and a coupling capacitor is formed only in the region where the power source throughholes are arranged with an intention to reduce noise.

Chip carrier

An integrated circuit is disclosed in which a plurality of semiconductor substrates are stacked in such a manner that an insulating board, provided with (1) structure, such as grooves, for transmitting a coolant so as to dissipate heat, and (2) an electrical interconnection member for electrically connecting adjacent semiconductor substrates, is sandwiched between semiconductor substrates. In order to attain the high-speed signal transmission between a semiconductor substrate and an insulating board, a signal current flows not only in a main surface of the semiconductor substrate but also in directions perpendicular to the main surface. The insulating board may be formed of an insulating silicon carbide plate which has a plurality of grooves filled with a metal.

High density integration of semiconductor circuit

An improved integrated circuit chips cooling module in which a cooling member having an inside space through which a coolant flows is attached to each of the integrated circuit chips by pressure welding or anchoring to effect cooling, wherein the improvement comprises providing coated portions for each portion of the surface of the coolant flow system where the coolant leakage may possibly take place, the coating of said coated portions comprising an organic or inorganic high-molecular weight compound curable by reacting with the coolant to keep the latter from leakage.

Integrated circuit chips cooling module having coolant leakage

An integrated circuit device comprising a wiring substrate on one surface of which integrated circuit chips are mounted, a power source substrate of a laminated structure provided in contact with the other surface of the wiring substrate and formed by alternately laminating a plurality of feeding conductor layers of a heat conductive metal and a plurality of electrically insulating layers of an electrically insulating material, and bonding together the laminated layers, a means for electrically connecting the wiring substrate and the power source substrate to each other, and a heat radiating means inserted in at least either the feeding conductor layers or the electrically insulating layers and adapted to radiate the heat, which occurs in the power source substrate, to the outside thereof. This integrated circuit device has a power source substrate of a remarkably high heat radiating efficiency, and is suitably used as an integrated circuit device having integrated circuit chips mounted with a high density on a wiring substrate therein.

Integrated circuit device

A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.

Signal transfer circuit for use in laminated multilayer electric circuit

A multilayer wiring board structure includes a plurality of conductor layers and insulation layers interleaved between each ones of the conductor layers. The conductor layers includes power (or ground) line layers and signal line layers, and one type of insulation layer having lower relative permittivity and another type of insulation layer having higher relative permittivity is used between power (ground) line layers interposed by signal line layer(s).

Hybrid multilayer wiring board

Growing community of inventors

Hanno, Japan

Minoru Yamada